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Lg 50PG4500 User Manual Page 116

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ISTRUZIONI PER REGOLAZIONE
1. Gamma applicazione
Questo foglio specifiche è valido per tutti i telai LD86F
prodotti dagli impianti TV LG in tutto il mondo.
2. Specifica.
2.1 Poiché questo non è un telaio caldo, non è necessario
utilizzare un trasformatore di isolamento. Tuttavia, l'uso di
un trasformatore di isolamento protegge gli strumenti di
test.
2.2 Eseguire la regolazione nella sequenza corretta.
2.3 Eseguire la regolazione alla temperatura di 25±5°C e
umidità relativa 65±10% in assenza di designazione
specificata.
2.4 La tensione di ingresso del ricevitore deve essere
compresa nell'intervallo 100~220V, 50/60Hz.
2.5 (5) Prima della regolazione, eseguire un Heat-Run per 5
minuti senza segnale RF.
3. Memoria canale
3.1 Metodo memoria canale
1) Premere il tasto IN-START nel telecomando di
regolazione.
2) Selezionare “Channel Recover” con il tasto ▲/▼(CH +/-) e
▶ premere (VOL+).
3) Al termine del recupero canali, l'impostazione verrà
disattivata e la spia LED andrà in modalità stand-by.
Prima della calibrazione AV ADC, eseguire “Tool
option 1”
4. Selezionare metodo si Tool option 1
4.1 Premere il tasto IN-START nel
telecomando di regolazione.
4.2 Selezionare “Tool option 1” con il tasto ▲/
▼ (CH +/-) e premere ■ (ENTER).
4.3
1)Selezionare “Maker” con il tasto ▲/▼ (CH+/-) e
cambiare il produttore del modulo e la classificazione
modulo applicata con ◀/▶(VOL+/-)
2) Selezionare “Inch” con il tasto ▲/▼ (CH+/-) e cambiare
il modulo in base ai pollici del modello.
3) Selezionare “Tool” con il tasto ▲/▼ (CH+/-) e cambiare
il nome strumento modulo in base al modello
• VITIAZ3 Module” con il tasto ▲/▼ (CH+/-) e selezionare in
base al modulo. (Vitiaz3 : 1, Altri: 0)
4.4 Do po aver cambiato Tool option 1 ,
premere il tasto EXIT.
5. Calibrazione ADC substrato
• Premere il tasto EXIT per eliminare la guida installazione prima
della regolazione dell'assieme PCB. Premere quindi il tasto
FRONT-AV sul telecomando regolazione.
(Cambio host RS-232C: G-Probe => PC. Cambio input: AV3)
5.1 Modalità calibrazione ADC
5.1.1 Regolazione di RF / AV
Modello: 202 / Pattern: 65
5.1.2 Regolazione componente
Modello: 215 / Pattern: 65
5.1.3 Regolazione di RGB
Modello: 60 / Pattern: 65
5.2 Protocollo calibrazione ADC [RS-232C]
Baud Rate : 115,200 bps
RS232C Host : PC
Echo : Nothing
• Se la calibrazione ADC non si regola nella linea di assieme
PCB, regolare la calibrazione ADC alla linea assieme finale.
Non premere il tasto IN STOP al termine dell'ispezione
funzione.
6. Calibrazione ADC
• Attenzione : - Host RS-232 controllo sistema deve essere “PC“
per regolazione.
- Prima della calibrazione AV ADC, eseguire la
“selezione modulo”
6.1 Regolazione di RF / AV / S-VIDEO
• Attrezzatura richiesta
- Telecomando per regolazione.
- Generatore pattern MSPG-925FS (con segnale video:
pattern 7 barre di colori in Fig. 1).
=> Modello: 202 / Pattern: 65
6.1.1 Metodo di bilanciamento colore auto RF / AV / S-VIDEO
(PAL_BGDHI).
1) Immettere il segnale Video: segnale 7 barre di colori in AV3.
2) Impostare la modalità Picture su Vivid nel menu Picture.
[Fig.1]
3) Premere il tasto ADJ sul telecomando per la regolazione.
4) Premere il tasto ▶ (Vol. +) per eseguire l'impostazione, quindi
si automatizza.
5) Sul lato inferiore dell'OSD, “AV OK” significa regolazione
completata.
ADC RF / AV / S-VIDEO Componente RGB-PC
PALJ
SEL INPUT AV3
MSPG925FS
Modello: 202 (PAL-BGDHI)
Pattern: 65
PAL
7 barre di colori
Modello:215 (720P)
Pattern:65
720P/50Hz
7 barre di colori
Modello: 60
(1024*768 60Hz)
Pattern: 65
N. Elemento CMD 1 CMD 2 Data0 Remark
Regol.
ADC
Regol. ADC a d 1 0
Lettura dati
Parametro ADC
(Diaplay princ.)
a d 2 0
Trasmissione 18 Byte (Display princ.)
: Input Display princ. e dati risoluzione
Parametro ADC
(Display sec.)
a d 2 1
Trasmissione 18 Byte (Display sec.)
: Input Display princ. e dati risoluzione
Dati digitali
(Display princ.)
a d 3 0
Dati digitali
(Display sec.)
a d 3 1
Scrittura
predef.
Parametro ADC
(Medio)
a d 4 0
Conferma
regolazione
a d 9 9
Usare per controllare ADC nel processo di
lavorazione WB assieme finale.
Modalit
regolazione
Regolazione
Mode In
a d 0 0
Quando si trasmette il comando di regolazione
Mode In, viene eseguito il comando di regolazione .
Regolazione
Mode Out
a d 9 0
6.2 Regolazione del componente
• Attrezzatura richiesta
- Telecomando per regolazione.
- Generatore pattern MSPG-925FS (con pattern di output
720p/50Hz YPbPr visualizzato in Fig. 2)
=> Modello: 215 / Pattern: 65
6.2.1 Metodo di bilanciamento colore Component automatico
1) Immettere il segnale barra 7 colori Component 720p/50Hz
(MSPG-925FS modello:215, pattern:65) in Component.
2) Impostare la modalità Picture su Vivid nel menu Picture.
[Fig.2]
3) Premere il tasto ADJ sul telecomando per la regolazione.
4) Premere il tasto ▶ (Vol. +) per eseguire l'impostazione, quindi
si automatizza.
5) Sul lato inferiore dell'OSD, “Component OK” significa
regolazione completata.
6.3 Regolazione di RGB
• Attrezzatura richiesta
- Telecomando per regolazione.
- Generatore pattern MSPG-925FS
(con pattern 100% 8 barre di colori XGA [1024*768] 60Hz
visualizzato in Fig. 3 )
6.3.1 Metodo di bilanciamento colore RGB automatico
1) Immettere il segnale 7 barre di colori PC 1024x768 @ 60Hz
(MSPG-925FS modello:60, pattern:65) in RGB.
(usare il cavo D-sub - Dsub)
2) Impostare la modalità Picture su Vivid nel menu Picture.
3) Premere il tasto ADJ sul telecomando per la regolazione.
[Fig.2]
4) Premere il tasto ▶ (Vol. +) per eseguire l'impostazione, quindi
si automatizza.
Sul lato inferiore dell'OSD, “RGB OK” significa regolazione
completata.
7. Bilanciamento del bianco
• Apparecchiatura del test
- Analizzatore colori (CA-210/CH.9)
-> Quando si regola la temperatura del colore LCD,
sull'analizzatore colori (CA-210), utilizzare il canale 9 con
compensazione di matrice (Bianco, Rosso, Verde, Blu
rivisti) per CS-1000 e regolare in base alla coordinata di
regolazione bilanciamento bianco specificata di seguito..
∆ Standard temperatura colore in base a CSM e Modulo
∆ Temperatura colore e coordinata regolazione bilanciamento
bianco
- PC (per comunicazione tramite RS-232C) -> vel. di trasf. dati
UART: 115200 bps
- Illuminazione Y AV: superiore 200 cd/m
2
(Tip: 350 cd/m
2
) ->
Applicazione a modalità Freddo
• Connessione immagine strumento di misurazione (su controllo
automatico)
: Viene utilizzato il PATTERN interno quando si controlla W/B.
Collegare a controller auto o premere sul telecomando IN-
START -> Accedere alla modalità di bilanciamento del bianco,
appare il pattern.
- Misurazione analizzatore colori: CS1000 o CA210(CH.9)
• Direzioni e interfaccia Autocontrollo
1. Regolare nel punto in cui l'afflusso luminoso come di un
proiettore è bloccato. (illuminazione inferiore a 10ux).
2. - In caso di PDP: Misurare e regolare dopo aver bloccato
l'analizzatore colori (CA-100+, CA-210 ) a lato del modulo.
- In caso di LCD: Far aderire strettamente l'analizzatore colori
( CA-210 ) al modulo a meno di 10 cm di distanza, tenerlo
sulla superficie del modulo e della sonda dell'analizzatore in
verticale.(80~100°).
3. Durata
- Attendere un po' dopo l'inizio, tenere acceso (non
interrompere l'alimentazione) ed eseguire heat-run per 15
minuti
- In caso di PDP, tenere il pattern bianco mediante pattern
interno.
- In caso di LCD, con ‘no signal’ o ‘full white pattern’ o altri,
controllare la retroilluminazione.
7.1 Bilanciamento del bianco autom.
(Impostare: RS-233 Host: PC, Vel. Baud:
115200bps, Download: Cortez).
; il pattern interno viene usato quando si controlla il
bilanciamento del bianco. Collegare come indicato nella figura
seguente e fare clic sul pulsante start sul programma di
esecuzione W/B. W/B elabora automaticamente Freddo ->
Medio -> Caldo nell'ordine.
Al termine di W/B, è possibile vedere ‘OK’ sul monitor del PC.
7.2 Bilanciamento manuale del bianco
; Uno di Gain R / Gain G / Gain B deve essere mantenuto su 80,
e regolare gli altri a meno di 80.
1) Premere ‘power on’ sul telecomando di controllo, impostare
heat run su bianco premendo , ed eseguire heat run per
almeno 5 minuti.
(Impostare: RS-233 Host: PC, Vel. Baud: 115200bps,
Download: Cortez).
2) Calibrazione Zero CA-210, e durante il controllo fissare il
sensore al centro della superficie del modulo LCD.
3) Fare doppio clic sul tasto In-start sul telecomando di controllo
e accedere a ‘white balance’.
4) Impostare il pattern di test e visualizzare il pattern interno. Il
controllo viene eseguito su tre temperature di colore, COOL,
MEDIUM, WARM. (Il controllo viene eseguito tre volte)
5) Se il GAIN R/G/B è 80 sull'OSD, si tratta della gamma FULL
DYNAMIC del modulo. Per controllare il bilanciamento del
bianco senza la saturazione della gamma FULL DYNAMIC e
DATA, tenere uno tra Gain R / Gain G / Gain B su 80, e
regolare gli altri a meno di 80.
* Temperatura colore: Freddo, Medio, Caldo
1. Se il GAIN R è impostato a 80
- Controllare GAIN G e GAIN B diminuendo da 80.
2. Se il GAIN B è impostato a 80
- Controllare GAIN R e GAIN G diminuendo da 80.
3. Se il GAIN G è impostato a 80
- Controllare GAIN R e GAIN B diminuendo da 80.
Uno di Gain R / Gain G / Gain B deve essere mantenuto su 80,
e regolare gli altri due a meno di 80.
(Se R/G/B GAIN sono tutti a 80, è la gamma FULL DYNAMIC
del modulo)
CSM
Cool
Medium
Warm
Plasma
11,000k
9,300k
6,500k
LCD
11,000k
9,300k
6,500k
Cool CS-1000 CA-210(CH 9)
x 0.276 0.276±0.002
y 0.283 0.283±0.002
uv 0.000
0.000
0.000
Medium CS-1000 CA-210(CH 9)
x
0.285
0.285±0.002
y 0.293 0.293±0.002
uv 0.000
Warm CS-1000 CA-210(CH 9)
x 0.313 0.313±0.002
y 0.329 0.329±0.002
uv 0.003 0.003
8. Impostare le informazioni (numero
di serie e nome modello)
1) Impostare secondo la figura seguente (configurato dopo
l'impostazione del bilanciamento del bianco) (Impostazione:
Premere il tasto IN-START nel telecomando di regolazione.
Selezionare “System Control 2” con il tasto ▲/▼(CH +/-) e
premere ■ (ENTER).
Utilizzando il telecomando regolazione, i valori RS-232 Host e
Vel. Baud e Download cambiano RS-232 Host:PC, Vel. Baud
:115200bps, Download:Cortez)
2) Scansione codice a barre
(1) Premere il pulsante di menu in modalità DTV.
Selezionare SETUP => Diagnostics => To set
(2) Controllare il numero di serie.
9. Premere il tasto IN-STOP
- Dopo aver impostato le informazioni, premere il tasto IN-STOP.
A/B/C/D/E/F/G/I
A(LMI DDR SDRAM Inferface)
I(V_LMI Video DDR SDRAM Interface)
C(Clock & Debug)
E(Transport Stream Interface)
B(EMI Flash)
D(GPIO, Alternate PINs)
G(Peripherals)
F(Video / Audio)
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
DDR_DATA[24]
V_DDR_DATA[13]
DDR_DATA[17]
V_DDR_DATA[15]
DDR_DATA[19]
V_DDR_DATA[20]
DDR_DATA[18]
V_DDR_DATA[22]
DDR_DATA[16]
V_DDR_DATA[21]
DDR_DATA[10]
V_DDR_DATA[23]
DDR_DATA[11]
V_DDR_DATA[31]
DDR_DATA[9]
V_DDR_DATA[30]
DDR_DATA[8]
V_DDR_DATA[29]
DDR_DATA[4]
DDR_DATA[3]
V_DDR_DATA[28]
DDR_DATA[7]
DDR_DATA[2]
V_DDR_DATA[26]
DDR_DATA[6]
DDR_DATA[1]
V_DDR_DATA[27]
DDR_DATA[5]
DDR_DATA[0]
V_DDR_DATA[25]
DDR_DATA[12]
V_DDR_DATA[24]
DDR_DATA[15]
V_DDR_DATA[18]
DDR_DATA[14]
V_DDR_DATA[19]
DDR_DATA[13]
V_DDR_DATA[17]
DDR_DATA[20]
V_DDR_DATA[16]
DDR_DATA[23]
V_DDR_ADDR[0-12]
V_DDR_DATA[10]
DDR_DATA[22]
V_DDR_DATA[11]
DDR_DATA[21]
DDR_ADDR[0-12]
V_DDR_DATA[9]
DDR_DATA[29]
V_DDR_DATA[8]
DDR_DATA[30]
V_DDR_DATA[4]
V_DDR_DATA[3]
DDR_DATA[31]
V_DDR_DATA[6]
V_DDR_DATA[2]
DDR_DATA[28]
V_DDR_DATA[5]
V_DDR_DATA[1]
DDR_DATA[25]
V_DDR_DATA[7]
V_DDR_DATA[0]
DDR_DATA[27]
V_DDR_DATA[12]
V_DDR_DATA[0-31]
DDR_DATA[26]
V_DDR_DATA[14]
DVO_DATA[0-23]
DVO_DATA[0]
DVO_DATA[1]
DVO_DATA[2]
DVO_DATA[3]
DVO_DATA[4]
DVO_DATA[5]
DVO_DATA[6]
DVO_DATA[7]
DVO_DATA[8]
DVO_DATA[9]
DVO_DATA[10]
DVO_DATA[11]
DVO_DATA[12]
DVO_DATA[13]
DVO_DATA[14]
DVO_DATA[15]
DVO_DATA[16]
DVO_DATA[17]
DVO_DATA[18]
DVO_DATA[19]
DVO_DATA[20]
DVO_DATA[21]
DVO_DATA[22]
DVO_DATA[23]
EMI_DATA[13]
EMI_DATA[7]
EMI_DATA[4]
EMI_DATA[14]
EMI_DATA[11]
EMI_DATA[6]
EMI_DATA[3]
EMI_DATA[15]
EMI_DATA[10]
EMI_DATA[12]
EMI_DATA[2]
EMI_DATA[5]
EMI_DATA[9]
EMI_DATA[0-15]
EMI_DATA[1]
EMI_DATA[8]
EMI_DATA[0]
EMI_ADDR[8]
EMI_ADDR[12]
EMI_ADDR[7]
EMI_ADDR[14]
EMI_ADDR[6]
EMI_ADDR[11]
EMI_ADDR[5]
EMI_ADDR[10]
EMI_ADDR[4]
EMI_ADDR[3]
EMI_ADDR[2]
EMI_ADDR[1]
EMI_ADDR[9]
EMI_ADDR[15]
EMI_ADDR[16]
EMI_ADDR[13]
EMI_ADDR[17]
EMI_ADDR[20]
EMI_ADDR[21]
EMI_ADDR[22]
EMI_ADDR[18]
EMI_ADDR[19]
DDR_ADDR[2]
DDR_ADDR[3]
DDR_ADDR[0]
DDR_ADDR[1]
DDR_ADDR[9]
DDR_ADDR[4]
DDR_ADDR[12]
DDR_ADDR[11]
DDR_ADDR[7]
DDR_ADDR[8]
DDR_ADDR[5]
DDR_ADDR[6]
DDR_ADDR[10]
V_DDR_ADDR[1]
V_DDR_ADDR[2]
V_DDR_ADDR[3]
V_DDR_ADDR[11]
V_DDR_ADDR[4]
V_DDR_ADDR[12]
V_DDR_ADDR[9]
V_DDR_ADDR[10]
V_DDR_ADDR[8]
V_DDR_ADDR[7]
V_DDR_ADDR[6]
V_DDR_ADDR[5]
V_DDR_ADDR[0]
LMI_ADDR[10]
V_LMI_ADDR[1]
V_LMI_DQM[2]
STC_JTAGnotRESET
/V_LMI_CAS
/LMI_BANK[1]
LMI_ADDR[11]
LMI_ADDR[4]
V_LMI_RD/WR
EMI_ADDR[6]
LMI_ADDR[8]
LMI_CKEN
V_DDR_ADDR[0-12]
V_DDR_BA[1]
STC_notASEBRK
DDR_DQM[1]
V_LMI_DQM[0]
AUD_PCMOUT3
/SYS_IRQ2
V_DDR_DQM[3]
LMI_ADDR[2]
LMI_DQM[0]
AUD_ANAL+
V_LMI_ADDR[3]
/V_LMI_CS[0]
V_LMI_CKEN
V_LMI_ADDR[11]
V_LMI_DQS[3]
/DDR_CS
/LMI_BANK[0]
AUDANA_GND
/V_DDR_CS
V_LMI_ADDR[1]
STC_notTRST
LMI_DQS[0]
LMI_ADDR[8]
/LMI_BANK[1]
V_LMI_DQS[2]
V_DDR_DQS[1]
EMI_ADDR[8]
V_LMI_ADDR[8]
R182
4.7K
OPT
LMI_DQM[3]
LMI_CKEN
V_LMI_ADDR[6]
STC_TCK
/DDR_RAS
V_LMI_ADDR[7]
EMI_ADDR[14]
V_LMI_ADDR[7]
/STi7100_Reset
LMI_ADDR[3]
LMI_DQM[1]
/V_LMI_CS[0]
AUD_ANAR+
R175
4.7K
OPT
R2101
10K
R185
4.7K
V_LMI_DQS[2]
V_LMI_CLK
R167
4.7K
/V_DDR_CAS
V_LMI_DQM[1]
LMI_DQS[3]
DDR_BA[0]
DDR_ADDR[0-12]
/V_LMI_BANK[0]
V_LMI_ADDR[4]
LMI_RD/WR
LMI_ADDR[9]
LMI_RD/WR
R163
4.7K
COMM_UART_TX
V_LMI_DQS[0]
R188
4.7K
OPT
/V_LMI_BANK[1]
/FE_RESET
EMI_ADDR[7]
LMI_DQM[0]
LMI_CLK
STC_TDO
DDR_DQM[0]
AUD_PCMOUT4
V_LMI_ADDR[9]
LMI_ADDR[6]
LMI_DQM[3]
AUD_ANAL-
SPDIF_STI_OUT
/V_LMI_CLK
STC_TriggerIn
V_LMI_ADDR[11]
V_LMI_ADDR[9]
LMI_DQS[2]
V_DDR_DQS[3]
DDR_BA[1]
I2C_SDA1
DDR_DQS[1]
R191
4.7K
OPT
V_LMI_ADDR[2]
/LMI_CS[0]
/LMI_RAS
LMI_ADDR[12]
COMM_UART_RX
/V_LMI_RAS
V_DDR_DQM[2]
/LMI_CLK
EMI_ADDR[5]
V_DDR_DQS[0]
STC_TMS
DDR_DQS[2]
EMI_ADDR[9]
V_DDR_DQM[1]
LMI_ADDR[7]
LMI_ADDR[7]
AUD_ANAR-
CI_TS_SEL
R181
4.7K
STC_TMS
LRCLK_DTV
/V_LMI_CLK
V_LMI_ADDR[10]
EMI_ADDR[1]
LMI_ADDR[3]
V_LMI_ADDR[8]
I2C_SCL1
DDR_CK0
V_LMI_DQS[1]
/LMI_RAS
/LMI_CS[0]
LMI_DQS[1]
R187
4.7K
R165
4.7K
SCLK_DTV
V_LMI_DQS[3]
LMI_ADDR[2]
V_DDR_DATA[0-31]
STC_notTRST
V_LMI_DQM[1]
DDR_DATA[0-31]
DDR_DQS[3]
R184
4.7K
EMI_ADDR[13]
R166
4.7K
47
R101
LMI_DQM[2]
V_LMI_DQM[3]
LMI_ADDR[4]
AUD_ANA_VBG
STC_TCK
STC_notASEBRK
CI_RST
V_LMI_CLK
/V_LMI_CAS
/FLASH_WP
LMI_ADDR[6]
EMI_ADDR[2]
/V_LMI_BANK[0]
R168
4.7K
V_LMI_ADDR[2]
/DDR_CK0
STC_TriggerIn
/DDR_WE
V_LMI_ADDR[4]
V_LMI_DQM[3]
LMI_DQS[0]
/LMI_CAS
LMI_DQS[2]
LMI_DQM[1]
V_LMI_RD/WR
/V_LMI_BANK[1]
R189
4.7K
OPT
/V_DDR_WE
STC_JTAGnotRESET
DDR_DQS[0]
EMI_ADDR[15]
LMI_ADDR[11]
AUD_PCMOUT4
LMI_ADDR[0]
/V_LMI_RAS
LMI_ADDR[5]
STC_TDI
V_LMI_CKEN
LMI_DQS[1]
V_LMI_ADDR[0]
EMI_ADDR[3]
V_LMI_ADDR[12]
R190
4.7K
/STi7100_Reset
LMI_CLK
STC_TDI
DDR_CKE
V_DDR_DQM[0]
V_LMI_DQM[2]
/LMI_CAS
EMI_ADDR[10]
R180
4.7K
R137
12K
LMI_DQS[3]
LMI_ADDR[0]
V_LMI_ADDR[12]
V_LMI_ADDR[3]
/V_DDR_RAS
V_DDR_CK0
V_LMI_ADDR[6]
DDR_DQM[3]
R183
4.7K
LMI_ADDR[5]
R161
4.7K
AUD_PCMOUT3
V_LMI_ADDR[0]
V_DDR_BA[0]
/LMI_BANK[0]
STC_TDO
LMI_ADDR[10]
V_DDR_CKE
LMI_ADDR[1]
V_DDR_DQS[2]
EMI_ADDR[4]
R186
4.7K
/LMI_CLK
R162
4.7K
LMI_ADDR[12]
DDR_DQM[2]
V_LMI_DQS[0]
V_LMI_ADDR[5]
EMI_ADDR[12]
/SYS_IRQ1
DVO_PIXCLK
LMI_ADDR[1]
LMI_DQM[2]
PCMDATA_DTV
LMI_ADDR[9]
V_LMI_ADDR[10]
V_LMI_DQS[1]
R164
4.7K
/V_DDR_CK0
V_LMI_DQM[0]
/DDR_CAS
V_LMI_ADDR[5]
L109
FI-C3216-103KJT
CVBS
DVO_DATA[0-23]
DVO_HSYNC
DVO_VSYNC
DEBUG_UART_TX
DEBUG_UART_RX
X101
27MHz
6
+VCC
1
V_CONTROL
2
TRI
5
NC
3
GND
4
OUTPUT
DVO_DE
R100
56
AUD_PCMOUT2
AUD_PCMOUT2
R169
4.7K
R196
1301%
E_DATA[2]
E_DATA[5]
E_DATA[15]
E_RD/WR
E_BusReq
E_DATA[13]
E_WAIT
E_DATA[9]
E_CSB
E_DATA[3]
E_CSA
E_DATA[6]
E_DATA[7]
E_BE[0]
E_DATA[0]
E_CSD
E_DATA[11]
E_DATA[4]
E_DATA[12]
E_DATA[8]
E_OE
E_BE[1]
E_DATA[10]
E_CSE
E_DATA[14]
E_BusGnt
E_DATA[1]
E_DATA[2]
E_DATA[14]
E_BE[1]
E_DATA[12]
E_DATA[9]
E_RD/WR
EMI_notCSD
EMI_BE0
EMI_DATA[0-15]
E_DATA[4]
E_BE[0]
E_DATA[8]
E_DATA[0]
E_OE
E_BusGnt
E_DATA[10]
E_BusReq
E_DATA[15]
E_CSB
EMI_notCSA
EMI_Wait
E_DATA[11]
E_CSA
E_DATA[3]
E_DATA[5]
E_WAIT
EMI_BusReq
EMI_notOE
EMI_RDnotWR
E_DATA[7]
E_DATA[1]
E_CSD
E_DATA[6]
EMI_BE1
E_DATA[13]
E_CSE
EMI_notBAA
EMI_BusReq
E_nLBA
E_nBAA
E_nBAA
E_nLBA
EMI_notLBA
EMI_ADDR[1-22]
E_CLKF
E_CLKF
AR126
33
AR127
33
AR123
33
AR124
33
AR125
33
AR116
33
AR121
33
AR119
33
AR117
33
AR120
33
AR122
33
AR118
33
AR129
33
DTV_RESET
PIO2B6
PIO2B7
CI_EN
EMI_Wait
VDD_HDMI
DDR_VREF
+2.6V_DDR
+3.3V_STi
+2.6V_V_DDR
+3.3V_STi
+3.3V_STi
V_DDR_VREF
+3.3V_STi
+3.3V_STi
+1.0V_STi7100
+1.0V_STi7100
R136
56
C126
0.1uF
C127
0.1uF
C119
0.1uF
C125
0.1uF
R158
47
R159
47
R118
10K
R119
10K
R122
10K
R103
10K
R121
10K
R108
10K
R117
10K
10K
R107
R125
10K
R120
10K
R197
10K
R123
10K
R2112
22
R2113
22
R2116
22
R2115
22
R2117
22
+2.6V_SATA
AR144
22
AR103
22
AR140
22
AR115
22
AR145
22
AR104
22
AR153
22
AR107
22
AR142
22
AR105
22
AR139
22
AR101
22
AR154
22
AR102
22
AR146
22
AR141
22
AR106
22
AR100
22
AR114
22
AR143
22
C124
10uF
16V
C130
1uF
50V
R2154
10K
R2109 7.5K
R2108
7.5K
X100
30MHz
C105
0.1uF
C106
0.1uF
C108
0.1uF
C107
0.01uF
C115
0.01uF
C114
0.1uF
C116
0.1uF
C117
0.1uF
C101
47pF
R2110
22
R2114
22
R149
47
R148
47
R156
47
R143
47
R146
47
R152
47
R155
47
R151
47
R140
47
R139
47
R147
47
R144
47
R2155
33
R2157
33
R124
10K
R126 10K
R127
10K
R2159
33
TS_DATA[3]
TS_DATA[7]
TS_DATA[5]
TS_DATA_SYN
TS_DATA_VAL
TS_DATA[4]
TS_DATA[0]
TS_DATA[2]
R2102 10K
TS_DATA[1]
TS_DATA[6]
TS_DATA_CLK
R2162 56
R2163 56
R2164 56
R2165 56
R2166 56
R2167 56
R2168 56
R2169 56
R2170 56
R2171 56
R2172
56
C131
0.1uF
GND
WDOG_Reset
R153
10K
R154
10K
R2173
22
R2174
22
R2175
22
R2176
22
R2177
22
R2178
22
R2179
22
R2180
22
R2181
22
R2182
22
R2183
22
R2184
22
R2185
22
R2186
22
R2187
22
R2188
22
R2189
22
R2190
22
R2192
22
R2193
22
R2194
22
R2195 22
R2196
22
R2197
22
R2198
22
R2199
22
R2200
22
R2201
22
R2202 22
R2203
22
R2204
22
R2205
22
R2206
22
R2208
22
R2209
22
R2210
22
R2211
22
R2212
22
R2107
270
R2214
22
R2215
22
R2216
22
R2217
22
R2218
22
R2219
22
R102
47K
C100
47pF
R2106
270
R2118
0
R2119
0
R2120
0
R2121
0
C134
0.1uF
C135
0.1uF
C132
0.1uF
C133
0.1uF
L100
LEMC3225T-6R8M
TP150
TP151
TP152
TP153
TP154
TP156
TP157
TP158
TP159
TP160
TP161
TP162
TP163
TP164
TP165
TP166
TP167
TP168
TP169
TP170
TP171
TP172
TP173
TP192
TP193
IC105
NL17SZ126DFT2G
3
2
4
15
IC106
NL17SZ126DFT2G
3
2
4
15
IC102
NL17SZ08DFT2G
GND
3
IN_A
2
4
OUT_Y
IN_B
1
5
VCC
C121
18pF
C122
18pF
IC100
STI7101
V1
LMI_DATA0
V2
LMI_DATA1
W1
LMI_DATA2
W2
LMI_DATA3
Y1
LMI_DATA4
Y2
LMI_DATA5
AA1
LMI_DATA6
AA2
LMI_DATA7
C1
LMI_DATA8
C2
LMI_DATA9
D1
LMI_DATA10
D2
LMI_DATA11
E1
LMI_DATA12
E2
LMI_DATA13
F1
LMI_DATA14
F2
LMI_DATA15
AD2
LMI_DATA16
AD1
LMI_DATA17
AE2
LMI_DATA18
AE1
LMI_DATA19
AF2
LMI_DATA20
AF1
LMI_DATA21
AG2
LMI_DATA22
AG1
LMI_DATA23
J2
LMI_DATA24
J1
LMI_DATA25
K2
LMI_DATA26
K1
LMI_DATA27
L2
LMI_DATA28
L1
LMI_DATA29
M2
LMI_DATA30
M1
LMI_DATA31
N1
LMI_CLK
P1
LMI_NOTCLK
P2
LMI_CKEN
AG12
DYCI15
AH13
DYCI14
AG11
DYCI13
AH11
DYCI12
AG14
DYCI11
AH12
DYCI10
AH14
DYCI9
AG15
DYCI8
L4
LMI_ADDR0
L3
LMI_ADDR1
K4
LMI_ADDR2
K3
LMI_ADDR3
H3
LMI_ADDR4
G4
LMI_ADDR5
G3
LMI_ADDR6
F4
LMI_ADDR7
F3
LMI_ADDR8
H4
LMI_ADDR9
M3
LMI_ADDR10
J3
LMI_ADDR11
J4
LMI_ADDR12
N3
LMI_NOTBANK0
M4
LMI_NOTBANK1
AB1
LMI_DQS0
G1
LMI_DQS1
AC2
LMI_DQS2
H1
LMI_DQS3
AB2
LMI_DQM0
G2
LMI_DQM1
AC1
LMI_DQM2
H2
LMI_DQM3
P3
LMI_NOTRAS
P4
LMI_NOTCAS
R3
LMI_RDNOTWR
N4
LMI_NOTCS0
R4
LMI_NOTCS1
R1
LMI_VREF
N2
LMI_REF
K7
LMI_GNDB_COMP
B16
V_LMI_DATA0
A16
V_LMI_DATA1
B17
V_LMI_DATA2
A17
V_LMI_DATA3
B18
V_LMI_DATA4
A18
V_LMI_DATA5
B19
V_LMI_DATA6
A19
V_LMI_DATA7
A2
V_LMI_DATA8
B2
V_LMI_DATA9
A3
V_LMI_DATA10
B3
V_LMI_DATA11
A4
V_LMI_DATA12
B4
V_LMI_DATA13
A5
V_LMI_DATA14
B5
V_LMI_DATA15
B22
V_LMI_DATA16
A22
V_LMI_DATA17
B23
V_LMI_DATA18
A23
V_LMI_DATA19
B24
V_LMI_DATA20
A24
V_LMI_DATA21
B25
V_LMI_DATA22
A25
V_LMI_DATA23
B8
V_LMI_DATA24
A8
V_LMI_DATA25
B9
V_LMI_DATA26
A9
V_LMI_DATA27
B10
V_LMI_DATA28
A10
V_LMI_DATA29
B11
V_LMI_DATA30
A11
V_LMI_DATA31
A14
V_LMI_CLK
A15
V_LMI_NOTCLK
B14
V_LMI_CKEN
R27
VIDOUTYC23
R28
VIDOUTYC22
T28
VIDOUTYC21
U27
VIDOUTYC20
P28
VIDOUTYC19
N28
VIDOUTYC18
M28
VIDOUTYC17
P27
VIDOUTYC16
AP30
SYSB_CLKOSC
A1
SYSA_CLKIN
AN30
SYSB_CLKIN
D26
SYSB_CLKIN_ALT
D20
RTC_CLKIN
D19
TMUCLK
C22
NOTTRST
C23
TDO
C20
NOTASEBRK
D23
TMS
C24
TDI
G20
DCUTRIGGEROUT
G21
DCUTRIGGERIN
D24
TCK
C21
NOTRESET
D21
WDOG_RESET_OUT
AL29
SYS_ITRQ0
AM29
SYS_ITRQ1
AL28
SYS_ITRQ2
AM30
SYS_ITRQ3
D22
NMI
C19
SYS_CLKOUT
AE3
TS0-DATA0
AD4
TS0_DATA1
AD3
TS0_DATA2
AC4
TS0_DATA3
AC3
TS0_DATA4
AB4
TS0_DATA5
AB3
TS0_DATA6
AA4
TS0_DATA7
AG3
TSBYTECLK0
AF4
TSPKTCLK0
AE4
TSPKTERR0
AF3
TSVALID0
AH3
TS1-DATA0/DYCI0
AG4
TS1_DATA1/DYCI1
AK1
TS1_DATA2/DYCI2
AK2
TS1_DATA3/DYCI3
AJ1
TS1_DATA4/DYCI4
AJ2
TS1_DATA5/DYCI5
AH1
TS1_DATA6/DYCI6
AH2
TS1_DATA7/DYCI7
AK3
TSBYTECLK1/DCKI
AJ4
TSPKTCLK1
AH4
TSPKTERR1/DHSI
AJ3
TSVALID1/DVSI
AP1
TS2-DATA0
AN2
TS2_DATA1
AN1
TS2_DATA2
AM3
TS2_DATA3
AM1
TS2_DATA4
AM2
TS2_DATA5
AL1
TS2_DATA6
AL2
TS2_DATA7
AN4
TSBYTECLK2
AP3
TSPKTCLK2
AP2
TSPKTERR2
AN3
TSVALID2
AN15
EMI_DATA0
AN9
EMI_DATA1
AP9
EMI_DATA2
AP11
EMI_DATA3
AP10
EMI_DATA4
AP12
EMI_DATA5
AP14
EMI_DATA6
AP13
EMI_DATA7
AP15
EMI_DATA8
AP16
EMI_DATA9
AN14
EMI_DATA10
AN12
EMI_DATA11
AN13
EMI_DATA12
AN11
EMI_DATA13
AN10
EMI_DATA14
AN8
EMI_DATA15
AP8
EMI_BE0/PCC_IOWR
AN7
EMI_BE1/EMI_ADDR[0]
AL7
EMI_NOTCSA
AM6
EMI_NOTCSB
AN6
EMI_NOTCSC
AP6
EMI_NOTCSD
AL6
EMI_NOTCSE
AP17
EMI_RDNOTWR
AP7
EMI_NOTOE/PCC_OE
AL19
EMI_WAIT
AP19
EMI_BUSREQ
AN19
EMI_BUSGNT
AL13
EMI_ADDR1
AL15
EMI_ADDR2
AM15
EMI_ADDR3
AL16
EMI_ADDR4
AM16
EMI_ADDR5
AL17
EMI_ADDR6
AM17
EMI_ADDR7
AM18
EMI_ADDR8
AL18
EMI_ADDR9
AM7
EMI_ADDR10
AL8
EMI_ADDR11
AM8
EMI_ADDR12
AL9
EMI_ADDR13
AM10
EMI_ADDR14
AL10
EMI_ADDR15
AM11
EMI_ADDR16
AM9
EMI_ADDR17
AL11
EMI_ADDR18
AL12
EMI_ADDR19
AM12
EMI_ADDR20
AM13
EMI_ADDR21
AL14
EMI_ADDR22
AM14
EMI_ADDR23
AN17
EMI_CLKF
AN16
PCC_WE/EMI_NLBA
AM19
PCC_IORD/EMI_NBAA
AN18
EMI_DMA_REQ0
AP18
EMI_DMA_REQ1
AN31
PIO0_0/SC_C4/SC0_DATAOUT/UART0_TXD
AP31
PIO0_1/SC_C7/SC0_DATAIN/UART0_RXD
AN32
PIO0_2/SC_C8
AP32
PIO0_3/SC0_CLK
AM32
PIO0_4/SC0_RESET/UART0_CTS
AP33
PIO0_5/SC0_COND_VCC/SC0_NSETVCC
AN33
PIO0_6/SC0_NOT_SETVPP/SC0_DIR/UART0_NOE
AP34
PIO0_7/SC0_DETECT/UART0_RTS
AN34
PIO1_0/SC1_DATAOUT/UART1_TXD
AM33
PIO1_1/SC1_DATAIN/UART1_RXD
AM34
PIO1_2/SC1_EXTCLK
AL33
PIO1_3/SC1_CLK
AL34
PIO1_4/UART1_CTS/NRSS_A_CLKOUT
AK33
PIO1_5/UART1_RTS/NRSS_A_DATAIN
AK34
PIO1_6/SC1_DIN/LONG_TIMEOUT_RST
AK32
PIO1_7/NRSS_A_DATAOUT
AJ34
PIO2_0/SSC0_SCL/DVO_BLANK
AJ33
PIO2_1/SSC0_MTSR/SSC0_MRST
AH34
PIO2_2/SSC0_MRST
AH33
PIO2_3/MAFE_HC1
AG34
PIO2_4/MAFE_DOUT
AG33
PIO2_5/MAFE_DIN
AF34
PIO2_6/MAFE_FS
AF33
PIO2_7/MAFE_SCLK
AJ31
PIO3_0/VTG_MAIN_HREF/SSC1_SCL
AJ32
PIO3_1/VTG_MAIN_REF/SSC1_MTSR/SSC1_MRST
AH31
PIO3_2/VTG_NTOP_BOT/SSC1_MRST
AH32
PIO3_3/IRB_IR_IN
AG31
PIO3_4/IRB_UHF_IN
AG32
PIO3_5/IRB_IR_DATAOUT
AF31
PIO3_6/LRB_IR_DATAOUT_OD
AF32
PIO3_7/PWM_CAPTURE0
AE34
PIO4_0/SSC2_SCL
AE33
PIO4_1/SSC2_MRST/SSC2_MTSR
AD34
PIO4_2/UART2_RXD
AD33
PIO4_3/UART2_TXD
AC34
PIO4_4/UART2_CTS
AC33
PIO4_5/UART2_RTS
AB34
PIO4_6/PWM_OUT_A
AB33
PIO4_7/PWM_OUT_B
AE31
PIO5_0/UART3_TXD
AE32
PIO5_1/UART3_RXD
AD31
PIO5_2/UART3_CTS
AD32
PIO5_3/UART3_RTS
AC31
PIO5_4/DISEQC_RX_DATA_IN
AC32
PIO5_5/DISEQC_TX_DATA_OUT
AB31
PIO5_6/QPP_PRT_OVRCR_I
AB32
PIO5_7/EHCL_PRT_PWR_O
G11
V_LMI_GNDB_COMP
B15
V_LMI_REF
C11
V_LMI_VREF
D17
V_LMI_NOTCS1
C17
V_LMI_NOTCS0
A26
V_LMI_RDNOTWR
C18
V_LMI_NOTCAS
D18
V_LMI_NOTRAS
B7
V_LMI_DQM3
B21
V_LMI_DQM2
B6
V_LMI_DQM1
B20
V_LMI_DQM0
A7
V_LMI_DQS3
A21
V_LMI_DQS2
A6
V_LMI_DQS1
A20
V_LMI_DQS0
C16
V_LMI_NOTBANK1
D16
V_LMI_NOTBANK0
D10
V_LMI_ADDR12
C9
V_LMI_ADDR11
D11
V_LMI_ADDR10
D9
V_LMI_ADDR9
C6
V_LMI_ADDR8
D7
V_LMI_ADDR7
C7
V_LMI_ADDR6
D8
V_LMI_ADDR5
C8
V_LMI_ADDR4
D14
V_LMI_ADDR3
C14
V_LMI_ADDR2
D15
V_LMI_ADDR1
C15
V_LMI_ADDR0
T33
TMDSTXCP
M33
TMDSREF
T34
TMDSTXCN
R33
TMDSTXOP
R34
TMDSTXON
P33
TMDSTX1P
P34
TMDSTX1N
N33
TMDSTX2P
N34
TMDSTX2N
AN23
USB_DP
AP23
USB_DM
AM23
USB_REF
AN27
SATA_TXP
AP27
SATA_TXN
AN28
SATA_RXP
AP28
SATA_RXN
AM27
SATA_REF
AN5
DAA_C1A
AP5
DAA_C2A
T31
VIDOUTYC0
T32
VIDOUTYC1
R31
VIDOUTYC2
R32
VIDOUTYC3
P31
VIDOUTYC4
P32
VIDOUTYC5
N31
VIDOUTYC6
N32
VIDOUTYC7
M31
VIDOUTYC8
M32
VIDOUTYC9
L31
VIDOUTYC10
L32
VIDOUTYC11
K31
VIDOUTYC12
K32
VIDOUTYC13
J31
VIDOUTYC14
J32
VIDOUTYC15
A34
VIDANACOUT1
C33
VIDANACVOUT1
B34
VIDANAYOUT1
E33
VIDANAROUT0
D32
VIDANAGOUT0
E34
VIDANABOUT0
D34
VIDANADUMPR0
C34
VIDANADUMPG0
D33
VIDANADUMPB0
C32
VIDANADUMPC1
A33
VIDANADUMPY1
B33
VIDANDDUMPCV1
A32
VIDANAREXT1
B32
VIDANAGNDREXT1
F34
VIDANAREXT0
F33
VIDANAGNDREXT0
D29
AUDDATAIN
D28
AUDSTRBIN
C29
AUDLRCLKIN
B28
AUDSPDIFOUT
D27
AUDPCMCLKOUT
C28
AUDSCLKOUT
C27
AUDLRCLKOUT
B27
AUDPCMOUT0
B26
AUDPCMOUT1
C26
AUDPCMOUT2
C25
AUDPCMOUT3
D25
AUDPCMOUT4
A30
AUDANAOUTPR
B30
AUDANAOUTMR
A29
AUDANAOUTPL
B29
AUDANAOUTML
A28
AUDANAIREFOUT
A27
AUDANAVBGIN
U32
VIDOUTHSYNC
U31
VIDOUTVSYNC
R2
LMI_DLL_VDD
J7
LMI_DLL_VSS
C10
V_LMI_DLL_VDD
G8
V_LMI_DLL_VSS
AR136
56
AR138
56
AR133
56
AR134
56
AR137
56
AR135
56
R2105
56
R2104
56
R160
56
+2.6V_VIDEO
C102
0.1uF
R131
12K
R130
12K
R2100
10K
R2221
2.7K
R2220
4.7K
+3.3V_STi
+3.3V_STi
+3.3V_STi
R2122
576
1%
R138
475
1%
R105
120K
R179
120K
L111
UBW2012-121F
L110
UBW2012-121F
C103
0.01uF
C104
0.01uF
CPU PIN Configuration #1/2
PLL1 CLOCK:Mode3
PLL2 CLOCK:Mode 0
RESERVED
MASTER/SLAVE
CPU PIN Configuration #2/2
RESETOUT MODE
EMI B/W:16(0)
RESERVED
I2C Channel Assign
CH1 : DVB-T, DVB-S2, LNBH21
CH2 : HDMI
CH0 : EEPROM
Must be ’0000’
EMI 32/64MB:32(0)
RESERVED
EMI/EMPI:7100compatable(00)
Plcae close to STi7101
Plcae close to STi7101
1. STX7109EX(1)
Must be near ST7109
H
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
C219
100pF
C216
100pF
C214
2200pF
L201
FI-A2012-391KJT
C228
100pF
L200
FI-A2012-391KJT
L208
FI-A2012-391KJT
C226
2200pF
FS0_GND
C233
100pF
+2.6V_VIDEO
+2.6V_STi7100
+1.0V_SATA
+2.6V_STi7100
+1.0V_STi7100
+2.6V_STi7100
+2.6V_STi7100
+2.6V_STi7100
+2.6V_STi7100
+1.0V_STi7100
+2.6V_SATA
+2.6V_DDR
+2.6V_V_DDR
+3.3V_STi7100I/O
+3.3V_STi7100I/O
C260
10uF
16V
C201
10uF
16V
VDD_HDMI
L227
HH-1M2012-600JT
L228
HH-1M2012-600JT
L214
HH-1M2012-600JT
C255
0.01uF
C205
0.01uF
C282
0.01uF
C277
0.01uF
C259
0.01uF
C215
0.01uF
C269
0.01uF
C247
0.01uF
C227
0.01uF
C263
0.01uF
C249
0.01uF
C207
0.01uF
C232
0.01uF
C283
0.01uF
C203
0.01uF
C213
0.01uF
C245
0.01uF
C251
0.01uF
C273
0.01uF
C253
0.01uF
C209
0.01uF
C211
0.01uF
C218
0.01uF
C250
0.1uF
C202
0.1uF
C276
0.1uF
C268
0.1uF
C285
0.1uF
C204
0.1uF
C254
0.1uF
C262
0.1uF
C252
0.1uF
C272
0.1uF
C284
0.1uF
C206
0.1uF
C258
0.1uF
C236
0.1uF
C210
0.1uF
C286
0.1uF
C287
0.1uF
C212
0.1uF
C208
0.1uF
R213
0
R203
0
C222
1uF
C221
1uF
C224
56000pF
C200
100uF
16V
C261
100uF
16V
C280
0.01uF
C281
0.01uF
C234
0.1uF
C238
0.1uF
C239
0.01uF
C235
0.01uF
C248
0.1uF
C244
0.1uF
C246
0.1uF
C242
0.1uF
C264
0.1uF
C243
0.01uF
C265
0.01uF
R202
0
C288
0.1uF
C289
0.1uF
C290
0.1uF
C291
0.1uF
C292
0.1uF
FS0_GND
FS0_GND
FS0_GND
C293
47uF
10V
C294
47uF
10V
C295
1uF
10V
OPT
L226
BLM18SG700TN1D
L223
BLM18SG700TN1D
L224
BLM18SG700TN1D
L213
BLM18SG700TN1D
L225
BLM18SG700TN1D
L219
BLM18SG700TN1D
L216
BLM18SG700TN1D
L217
BLM18SG700TN1D
L220
BLM18SG700TN1D
L221
BLM18SG700TN1D
L218
BLM18SG700TN1D
L215
BLM18SG700TN1D
C240
0.1uF
C241
0.01uF
C225
4.7uF
C257
4.7uF
C256
4.7uF
C296
4.7uF
C274
0.1uF
AUDANA_GND
TP200
TP201
TP202
TP203
TP204
TP205
TP206
TP207
TP208
TP209
TP210
TP211
TP212
TP213
TP214
TP215
TP216
TP217
TP218
TP219
C278
10uF
6.3V
C279
10uF
6.3V
IC100
STI7101
AP25
SATA_VDDOSC2V5
R19
GND1V0_27
F19
GNDE_1
AG8
VDD1V0_1
AN26
SATA_VDDOSC1
AH27
SATA_VSSOSC_1
AM25
SATA_VDDR0
AL25
SATA_VDDR1
AN29
SATA_VSSR
AN25
SATA_VDDT0
AP26
SATA_VDDT1
AP29
SATA_VSST
AM26
SATA_VDDDLL_1
AM28
SATA_VSSDLL_1
AL26
SATA_VDDREF
AL27
SATA_VSSREF
AP22
USB_VDDBS
AN22
USB_VDDP
AL22
USB_VSSBS
AM22
USB_VSSP
K34
FS0_VDDD
J34
FS0_GNDD
B1
CKGA_PLL1_DVDDPLL1V0
D3
CKGA_PLL2_DVDDPLL1V0
G7
CKGA_PLL1_DGNDPLL1V0
H7
CKGA_PLL2_DGNDPLL1V0
L33
CKGB_4FS1_VDDD
L34
CKGB_4FS0_VDDD
H34
CKGB_4FS0_GNDD
H33
CKGB_4FS1_GNDD
K33
DVDDDPLL80V0
J33
DGNDPLL80V0
M34
TMDS_VDD
AA31
TMDS_VDDC0
AA32
TMDS_VDDC1
AA33
TMDS_VDDC2
Y31
TMDS_VDDCK
AA34
TMDS_VDDP
Y34
TMDS_VDDX
Y32
TMDS_VDDSL
Y33
TMDS_VDDD
V31
TMDS_VSSC0
V32
TMDS_VSSC1
V33
TMDS_VSSC2
W31
TMDS_VSSCK
V34
TMDS_VSSP
W34
TMDS_VSSX
W32
TMDS_VSSSL
W33
TMDS_VSSD
N13
GND1V0_1
AB14
GND1V0_2
AB21
GND1V0_3
AB22
GND1V0_4
AF27
GND1V0_5
AF28
GND1V0_6
AF29
GND1V0_7
AG27
GND1V0_8
AG26
GND1V0_9
AG28
GND1V0_10
N14
GND1V0_11
N21
GND1V0_12
N22
GND1V0_13
P13
GND1V0_14
P14
GND1V0_15
P15
GND1V0_16
P16
GND1V0_17
P19
GND1V0_18
P20
GND1V0_19
P21
GND1V0_20
P22
GND1V0_21
R14
GND1V0_22
R15
GND1V0_23
R16
GND1V0_24
R17
GND1V0_25
R18
GND1V0_26
R20
GND1V0_28
R21
GND1V0_29
T14
GND1V0_30
T15
GND1V0_31
T16
GND1V0_32
T17
GND1V0_33
T18
GND1V0_34
T19
GND1V0_35
T20
GND1V0_36
T21
GND1V0_37
U15
GND1V0_38
U16
GND1V0_39
U17
GND1V0_40
U18
GND1V0_41
U19
GND1V0_42
U20
GND1V0_43
V15
GND1V0_44
V16
GND1V0_45
V17
GND1V0_46
V18
GND1V0_47
V19
GND1V0_48
V20
GND1V0_49
W14
GND1V0_50
W15
GND1V0_51
W16
GND1V0_52
W17
GND1V0_53
W18
GND1V0_54
W19
GND1V0_55
W20
GND1V0_56
W21
GND1V0_57
Y14
GND1V0_58
Y15
GND1V0_59
Y16
GND1V0_60
Y17
GND1V0_61
Y18
GND1V0_62
Y19
GND1V0_63
Y20
GND1V0_64
Y21
GND1V0_65
AA13
GND1V0_66
AA14
GND1V0_67
AA15
GND1V0_68
AA16
GND1V0_69
AA19
GND1V0_70
AA20
GND1V0_71
AA21
GND1V0_72
AA22
GND1V0_73
AB13
GND1V0_74
F18
GNDE_2
W29
GNDE_3
W28
GNDE_4
F17
GNDE_5
F16
GNDE_6
F11
GNDE_7
F10
GNDE_8
F9
GNDE_9
F8
GNDE_10
F7
GNDE_11
F6
GNDE_12
Y29
GNDE_13
Y28
GNDE_14
Y27
GNDE_15
G6
GNDE_16
G23
GNDE_17
G22
GNDE_18
G19
GNDE_19
G18
GNDE_20
G17
GNDE_21
G16
GNDE_22
G10
GNDE_23
H14
V_LMI_VDDE2V5_1
F23
GNDE_24
F22
GNDE_25
F21
GNDE_26
F20
GNDE_27
H6
GNDE_28
H8
GNDE_29
H15
GNDE_30
H20
GNDE_31
L6
GNDE_32
M6
GNDE_33
L7
GNDE_34
H21
GNDE_35
M7
GNDE_36
J6
GND_AF5
K6
GND_AF4
J8
GND_AF3
H23
GND_AF2
AA3
VDDE2V5_1
W3
VDDE2V5_2
Y3
VDDE2V5_3
W4
VDDE2V5_4
V3
VDDE2V5_5
G29
GND_ANA_1
H26
GND_ANA_2
G26
GNDE_AUD_ANA
D30
AUD_GNDAS
C30
AUD_GNDA
G27
AUD_VCCA
H28
VDDE2V5_AUD_ANA
J28
GNDE_VID_ANA
D31
DA_SD_GNDA
C31
DA_HD_GNDA
B31
DA_SD_VCCA
A31
DA_HD_VCCA
E31
VDDE2V5_VID_ANA_1
J27
GNDE_PLL80_ANA
H31
GNDE_4FS_ANA
M27
AGNDPLL80V0
H32
CKGB_4FS1_GNDA
K28
CKGB_4FS0_GNDA
G31
VDDE2V5_PLL80_ANA
G32
VDDE2V5_4FS_ANA
G28
AVDDPLL80V0
G33
CKGB_4FS1_VCCA
G34
CKGB_4FS0_VCCA
H9
CKGA_PLL2_AGNDPLL2V5
G9
CKGA_PLL1_AGNDPLL2V5
D6
CKGA_PLL2_AVDDPLL2V5
C4
CKGA_PLL1_AVDDPLL2V5
D5
CKGA_PLL_VDDE2V5
L27
GNDE_FS0_ANA
L28
FS0_GNDA
F31
FS0_VCCA
F32
VDDE2V5_FS0_ANA
AL24
USB_VSSP2V5
AM24
USB_VSSC2V5
AP24
USB_VDDP2V5
AN24
USB_VDDC2V5
U33
TMDS_GNDE3V3
U34
TMDS_VDDE3V3
AL32
GNDE3V3_DIG3_1
AM31
GNDE3V3_DIG3_2
AL31
GNDE3V3_DIG3_3
AL30
GNDE3V3_DIG3_4
AK31
GNDE3V3_DIG3_5
AJ29
GNDE3V3_DIG3_6
AJ28
GNDE3V3_DIG3_7
AH29
GNDE3V3_DIG3_8
AC6
VDDE3V3_DIG3_1
AB7
VDDE3V3_DIG3_2
AB6
VDDE3V3_DIG3_3
AC8
VDDE3V3_DIG3_4
AC7
VDDE3V3_DIG3_5
AH10
VDDE3V3_DIG3_6
AD8
VDDE3V3_DIG3_7
AD7
VDDE3V3_DIG3_8
AD6
VDDE3V3_DIG3_9
AJ18
VDDE3V3_DIG3_10
AJ14
VDDE3V3_DIG3_11
AJ13
VDDE3V3_DIG3_12
AJ12
VDDE3V3_DIG3_13
AJ11
VDDE3V3_DIG3_14
AJ10
VDDE3V3_DIG3_15
AH21
VDDE3V3_DIG3_16
AH20
VDDE3V3_DIG3_17
AJ19
VDDE3V3_DIG3_18
AH19
VDDE3V3_DIG3_19
AH18
VDDE3V3_DIG3_20
AC27
VDD1V0_2
AC29
VDD1V0_3
AC28
VDD1V0_4
AF8
VDD1V0_5
AB29
VDD1V0_6
AB28
VDD1V0_7
AB20
VDD1V0_8
AB19
VDD1V0_9
AB16
VDD1V0_10
AB15
VDD1V0_11
AA29
VDD1V0_12
AA28
VDD1V0_13
AA27
VDD1V0_14
AA8
VDD1V0_15
AA7
VDD1V0_16
AA6
VDD1V0_17
Y22
VDD1V0_18
Y13
VDD1V0_19
Y8
VDD1V0_20
Y7
VDD1V0_21
Y6
VDD1V0_22
W22
VDD1V0_23
W13
VDD1V0_24
T22
VDD1V0_25
T13
VDD1V0_26
R22
VDD1V0_27
R13
VDD1V0_28
N20
VDD1V0_29
N19
VDD1V0_30
N16
VDD1V0_31
N15
VDD1V0_32
H18
VDD1V0_33
H17
VDD1V0_34
E4
VDD1V0_35
E3
VDD1V0_36
AJ22
VDD1V0_37
AH24
VDD1V0_38
AH23
VDD1V0_39
AJ24
VDD1V0_40
AJ23
VDD1V0_41
AH22
VDD1V0_42
AG24
VDD1V0_43
AG23
VDD1V0_44
AG9
VDD1V0_45
C3
VDD1V0_46
C5
VDD1V0_47
D4
VDD1V0_48
AL23
USB_VDDB3V3
AH26
SATA_VSSOSC_2
AH25
SATA_VDDDLL_2
AH28
SATA_VSSDLL_2
E32
VDDE2V5_VID_ANA_2
H27
GND_ANA_3
H29
GND_ANA_4
J29
GND_ANA_5
K29
GND_ANA_6
L29
GND_ANA_7
M29
GND_ANA_8
AJ25
VDD1V0_49
AJ26
VDD1V0_50
AJ27
VDD1V0_51
AG29
GND1V0_75
Y4
VDDE2V5_6
V4
VDDE2V5_7
AJ20
VDDE3V3_DIG3_21
AJ21
VDDE3V3_DIG3_22
AL20
VDDE3V3_DIG3_23
AL21
VDDE3V3_DIG3_24
AM20
VDDE3V3_DIG3_25
AM21
VDDE3V3_DIG3_26
AN20
VDDE3V3_DIG3_27
AN21
VDDE3V3_DIG3_28
AP20
VDDE3V3_DIG3_29
AP21
VDDE3V3_DIG3_30
AD27
VDDE3V3_DIG3_31
AD28
VDDE3V3_DIG3_32
AD29
VDDE3V3_DIG3_33
AE28
VDDE3V3_DIG3_34
AE29
VDDE3V3_DIG3_35
P29
VDDE3V3_DIG3_36
R29
VDDE3V3_DIG3_37
T29
VDDE3V3_DIG3_38
U28
VDDE3V3_DIG3_39
U29
VDDE3V3_DIG3_40
V27
VDDE3V3_DIG3_41
V28
VDDE3V3_DIG3_42
V29
VDDE3V3_DIG3_43
F24
VDDE3V3_DIG3_44
F25
VDDE3V3_DIG3_45
F26
VDDE3V3_DIG3_46
F27
VDDE3V3_DIG3_47
F28
VDDE3V3_DIG3_48
F29
VDDE3V3_DIG3_49
G24
VDDE3V3_DIG3_50
G25
VDDE3V3_DIG3_51
H24
VDDE3V3_DIG3_52
N6
GNDE_37
N7
GNDE_38
P6
GNDE_39
P7
GNDE_40
V6
GNDE_41
V7
GNDE_42
W6
GNDE_43
W7
GNDE_44
AE6
GNDE_45
AE7
GNDE_46
AF6
GNDE_47
AF7
GNDE_48
AG6
GNDE_49
AG7
GNDE_50
AG17
GNDE_51
AG18
GNDE_52
AG20
GNDE_53
AG21
GNDE_54
AH6
GNDE_55
AH7
GNDE_56
AH8
GNDE_57
AH9
GNDE_58
AH15
GNDE_59
AH16
GNDE_60
AH17
GNDE_61
AJ6
GNDE_62
AJ7
GNDE_63
AJ8
GNDE_64
AJ9
GNDE_65
AJ15
GNDE_66
AJ16
GNDE_67
AJ17
GNDE_68
AK4
GNDE_69
AL3
GNDE_70
AL4
GNDE_71
AL5
GNDE_72
AM4
GNDE_73
AM5
GNDE_74
AP4
GNDE_75
L8
LMI_VDDE2V5_1
M8
LMI_VDDE2V5_2
P8
LMI_VDDE2V5_3
R6
LMI_VDDE2V5_4
R7
LMI_VDDE2V5_5
R8
LMI_VDDE2V5_6
T2
LMI_VDDE2V5_7
T4
LMI_VDDE2V5_8
T6
LMI_VDDE2V5_9
T1
LMI_VDDE2V5_10
T3
LMI_VDDE2V5_11
T7
LMI_VDDE2V5_12
U1
LMI_VDDE2V5_13
U2
LMI_VDDE2V5_14
U3
LMI_VDDE2V5_15
U4
LMI_VDDE2V5_16
U6
LMI_VDDE2V5_17
U7
LMI_VDDE2V5_18
U8
LMI_VDDE2V5_19
V8
LMI_VDDE2V5_20
F13
V_LMI_VDDE2V5_2
F12
V_LMI_VDDE2V5_3
D13
V_LMI_VDDE2V5_4
D12
V_LMI_VDDE2V5_5
C13
V_LMI_VDDE2V5_6
C12
V_LMI_VDDE2V5_7
B13
V_LMI_VDDE2V5_8
B12
V_LMI_VDDE2V5_9
A13
V_LMI_VDDE2V5_10
A12
V_LMI_VDDE2V5_11
F14
V_LMI_VDDE2V5_12
F15
V_LMI_VDDE2V5_13
G12
V_LMI_VDDE2V5_14
G13
V_LMI_VDDE2V5_15
G14
V_LMI_VDDE2V5_16
G15
V_LMI_VDDE2V5_17
H11
V_LMI_VDDE2V5_18
H12
V_LMI_VDDE2V5_19
N29
GND_ANA_9
L222
BLM18SG700TN1D
C270
0.1uF
C266
0.1uF
C271
0.01uF
C267
0.01uF
+3.3V_STi
+3.3V_STi
FS0_GND
2. STX7109EX(2)
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
V_DDR_DATA[25]
V_DDR_DATA[13]
V_DDR_ADDR[9]
DDR_DATA[10]
DDR_DATA[22]
DDR_ADDR[3]
V_DDR_DATA[14]
V_DDR_DATA[5]
DDR_ADDR[12]
DDR_DATA[3]
V_DDR_DATA[27]
DDR_DATA[24]
V_DDR_ADDR[3]
DDR_ADDR[2]
V_DDR_ADDR[10]
V_DDR_DATA[7]
V_DDR_DATA[28]
DDR_DATA[25]
V_DDR_ADDR[6]
V_DDR_DATA[24]
DDR_DATA[25]
V_DDR_DATA[30]
V_DDR_ADDR[2]
DDR_ADDR[1]
DDR_ADDR[9]
V_DDR_DATA[16]
DDR_DATA[14]
DDR_DATA[4]
DDR_ADDR[11]
DDR_ADDR[0]
V_DDR_DATA[28]
DDR_DATA[26]
V_DDR_ADDR[1]
V_DDR_ADDR[1]
DDR_ADDR[0]
V_DDR_DATA[17]
V_DDR_DATA[27]
V_DDR_DATA[29]
DDR_DATA[28]
V_DDR_ADDR[12]
V_DDR_ADDR[0]
DDR_DATA[2]
DDR_ADDR[10]
DDR_ADDR[5]
V_DDR_DATA[18]
DDR_DATA[8]
DDR_DATA[6]
V_DDR_DATA[30]
DDR_DATA[29]
DDR_DATA[15]
V_DDR_DATA[22]
DDR_DATA[12]
V_DDR_ADDR[10]
DDR_DATA[29]
DDR_ADDR[3]
DDR_DATA[1]
V_DDR_ADDR[10]
DDR_ADDR[0]
V_DDR_DATA[19]
V_DDR_ADDR[5]
DDR_DATA[9]
V_DDR_DATA[9]
V_DDR_DATA[24]
DDR_DATA[0]
DDR_DATA[20]
DDR_DATA[30]
V_DDR_DATA[4]
V_DDR_DATA[23]
DDR_ADDR[6]
DDR_DATA[0]
DDR_ADDR[1]
V_DDR_DATA[20]
DDR_DATA[13]
DDR_DATA[1]
DDR_DATA[23]
DDR_DATA[31]
DDR_DATA[26]
V_DDR_DATA[16]
DDR_DATA[30]
DDR_DATA[4]
V_DDR_DATA[21]
DDR_ADDR[1]
DDR_DATA[7]
DDR_DATA[9]
V_DDR_DATA[17]
DDR_DATA[5]
DDR_DATA[0-31]
DDR_DATA[31]
DDR_DATA[10]
DDR_DATA[27]
V_DDR_DATA[18]
V_DDR_ADDR[11]
V_DDR_ADDR[4]
V_DDR_ADDR[7]
DDR_ADDR[2]
DDR_DATA[27]
DDR_DATA[11]
DDR_ADDR[7]
V_DDR_DATA[19]
DDR_DATA[5]
DDR_ADDR[3]
V_DDR_DATA[8]
DDR_DATA[8]
DDR_DATA[12]
V_DDR_DATA[20]
V_DDR_ADDR[3]
DDR_DATA[28]
V_DDR_DATA[0-31]
DDR_DATA[22]
DDR_DATA[13]
V_DDR_DATA[0]
DDR_ADDR[0-12]
V_DDR_DATA[21]
DDR_DATA[20]
DDR_ADDR[9]
DDR_DATA[21]
V_DDR_ADDR[5]
DDR_DATA[18]
DDR_DATA[14]
V_DDR_DATA[15]
DDR_ADDR[11]
V_DDR_DATA[1]
V_DDR_DATA[0-31]
DDR_DATA[24]
DDR_DATA[19]
DDR_DATA[7]
DDR_DATA[0-31]
DDR_DATA[15]
DDR_DATA[21]
V_DDR_ADDR[7]
DDR_DATA[18]
V_DDR_DATA[5]
DDR_ADDR[2]
V_DDR_DATA[26]
DDR_DATA[17]
V_DDR_DATA[6]
V_DDR_DATA[29]
DDR_DATA[16]
DDR_ADDR[4]
DDR_ADDR[12]
DDR_ADDR[7]
DDR_DATA[3]
V_DDR_DATA[22]
V_DDR_DATA[31]
DDR_DATA[17]
V_DDR_ADDR[11]
V_DDR_DATA[23]
V_DDR_DATA[3]
DDR_ADDR[0-12]
V_DDR_DATA[10]
V_DDR_ADDR[1]
V_DDR_ADDR[8]
V_DDR_ADDR[0-12]
V_DDR_DATA[9]
DDR_ADDR[5]
V_DDR_DATA[7]
DDR_ADDR[6]
V_DDR_ADDR[3]
DDR_ADDR[4]
DDR_ADDR[10]
V_DDR_DATA[11]
V_DDR_ADDR[8]
DDR_ADDR[12]
V_DDR_ADDR[11]
V_DDR_ADDR[6]
V_DDR_DATA[31]
V_DDR_DATA[8]
DDR_ADDR[11]
V_DDR_ADDR[0]
DDR_ADDR[10]
V_DDR_ADDR[2]
DDR_DATA[23]
V_DDR_DATA[1]
DDR_DATA[19]
V_DDR_DATA[14]
DDR_ADDR[9]
V_DDR_ADDR[5]
DDR_ADDR[8]
V_DDR_DATA[11]
V_DDR_DATA[0]
V_DDR_ADDR[2]
V_DDR_DATA[12]
DDR_ADDR[8]
V_DDR_DATA[10]
V_DDR_DATA[13]
DDR_ADDR[8]
DDR_DATA[6]
V_DDR_ADDR[0]
DDR_ADDR[7]
V_DDR_DATA[2]
V_DDR_DATA[15]
V_DDR_ADDR[8]
DDR_DATA[16]
DDR_ADDR[6]
V_DDR_DATA[3]
V_DDR_ADDR[9]
V_DDR_DATA[25]
V_DDR_ADDR[12]
DDR_DATA[11]
V_DDR_DATA[12]
V_DDR_ADDR[6]
V_DDR_ADDR[4]
DDR_ADDR[5]
V_DDR_DATA[6]
DDR_DATA[2]
V_DDR_ADDR[7]
V_DDR_DATA[26]
V_DDR_ADDR[12]
V_DDR_DATA[2]
DDR_ADDR[4]
V_DDR_DATA[4]
V_DDR_ADDR[9]
V_DDR_ADDR[4]
DVO_DATA[0]
DVO_DATA[1]
DVO_DATA[2]
DVO_DATA[3]
DVO_DATA[4]
DVO_DATA[5]
DVO_DATA[6]
DVO_DATA[7]
DVO_DATA[8]
DVO_DATA[9]
DVO_DATA[10]
DVO_DATA[11]
DVO_DATA[12]
DVO_DATA[13]
DVO_DATA[14]
DVO_DATA[15] DVO_DATA[23]
DVO_DATA[22]
DVO_DATA[21]
DVO_DATA[20]
DVO_DATA[19]
DVO_DATA[18]
DVO_DATA[17]
DVO_DATA[16]
BDATA[0]
BDATA[1]
BDATA[2]
BDATA[3]
BDATA[4]
BDATA[5]
BDATA[6]
BDATA[7]
BDATA[8]
BDATA[9]
BDATA[10]
BDATA[11]
BDATA[12]
BDATA[13]
BDATA[14]
BDATA[15]
BDATA[16]
BDATA[17]
BDATA[18]
BDATA[19]
BDATA[20]
BDATA[21]
BDATA[22]
BDATA[23]
EMI_ADDR[16]
EMI_ADDR[15]
EMI_ADDR[14]
EMI_ADDR[13]
EMI_ADDR[12]
EMI_ADDR[11]
EMI_ADDR[10]
EMI_ADDR[9]
EMI_ADDR[20]
EMI_ADDR[21]
EMI_ADDR[22]
EMI_ADDR[17]
EMI_ADDR[1]
EMI_DATA[15]
EMI_DATA[7]
EMI_DATA[14]
EMI_DATA[6]
EMI_DATA[13]
EMI_DATA[5]
EMI_DATA[12]
EMI_DATA[4]
EMI_DATA[11]
EMI_DATA[3]
EMI_DATA[10]
EMI_DATA[2]
EMI_DATA[9]
EMI_DATA[1]
EMI_DATA[8]
EMI_DATA[0]
EMI_ADDR[19]
EMI_ADDR[18]
EMI_ADDR[8]
EMI_ADDR[7]
EMI_ADDR[6]
EMI_ADDR[5]
EMI_ADDR[4]
EMI_ADDR[3]
EMI_ADDR[2]
/DDR_CK0 /DDR_WE /V_DDR_WE
/V_DDR_CAS
DDR_DQM[3]
V_DDR_DQS[1]
DDR_DQM[1]
/DDR_CS
V_DDR_BA[0]
DDR_BA[0]
V_DDR_CK0
V_DDR_BA[0]
V_DDR_DQM[0]
/DDR_CS
/V_DDR_CAS
/V_DDR_WE
V_DDR_BA[0]
V_DDR_DQS[1]
V_DDR_DQS[3]
/DDR_CAS
DDR_DQS[1]
DDR_DQM[3]
DDR_BA[1]
V_DDR_CKE
/DDR_CK0
/V_DDR_CS
V_DDR_DQS[2]
DDR_CK0
/DDR_CK0
/DDR_RAS
/DDR_CAS
DDR_DQS[0]
/V_DDR_RAS
DDR_DQM[1]
DDR_BA[1]
/V_DDR_WE
V_DDR_DATA[0-31]
DDR_CKE
V_DDR_DQS[0]
/V_DDR_CAS
I2C_SDA1
V_DDR_DQM[2]
DDR_DQS[0]
DDR_DQS[2]
V_DDR_CKE
DDR_BA[1]
DDR_DQM[0]
/V_DDR_CS
/V_DDR_CS
/V_DDR_CK0
V_DDR_DQS[2]
/DDR_WE
DDR_DQS[3]
DDR_CKE
/V_DDR_RAS
V_DDR_DQM[2]
V_DDR_BA[1]
/DDR_RAS
DDR_BA[0]
DDR_CK0
DDR_DQS[3]
DDR_DATA[0-31]
V_DDR_DQM[1]
DDR_CKE
/V_DDR_CK0
DDR_DQS[2]
V_DDR_DQM[3]
DDR_DQS[1]
V_DDR_DQM[1]
V_DDR_CKE
V_DDR_DQM[3]
I2C_SCL1
DDR_DQM[0]
DDR_CK0
V_DDR_CK0
V_DDR_DQM[0]
/DDR_WE
DDR_ADDR[0-12]
/DDR_CS
DDR_BA[0]
V_DDR_ADDR[0-12]
V_DDR_DQS[3]
/DDR_CAS
DDR_DQM[2]
V_DDR_BA[1]
V_DDR_DQS[0]
/V_DDR_CK0
V_DDR_CK0
/V_DDR_RAS
V_DDR_BA[1]
DDR_DQM[2]
/DDR_RAS
IC311
74LVC541A(PW)
3
A1
2
A0
4
A2
1
OE1
6
A4
5
A3
7
A5
8
A6
9
A7
10
GND
11
Y7
12
Y6
13
Y5
14
Y4
15
Y3
16
Y2
17
Y1
18
Y0
19
OE2
20
VCC
IC312
74LVC541A(PW)
3
A1
2
A0
4
A2
1
OE1
6
A4
5
A3
7
A5
8
A6
9
A7
10
GND
11
Y7
12
Y6
13
Y5
14
Y4
15
Y3
16
Y2
17
Y1
18
Y0
19
OE2
20
VCC
IC313
74LVC541A(PW)
3
A1
2
A0
4
A2
1
OE1
6
A4
5
A3
7
A5
8
A6
9
A7
10
GND
11
Y7
12
Y6
13
Y5
14
Y4
15
Y3
16
Y2
17
Y1
18
Y0
19
OE2
20
VCC
DVO_DATA[0-23]
IC314
74LVC541A(PW)
3
A1
2
A0
4
A2
1
OE1
6
A4
5
A3
7
A5
8
A6
9
A7
10
GND
11
Y7
12
Y6
13
Y5
14
Y4
15
Y3
16
Y2
17
Y1
18
Y0
19
OE2
20
VCC
DVO_HSYNC
DVO_VSYNC
DVO_PIXCLK
DVO_DE
3_STATE_BUFFER 3_STATE_BUFFER
3_STATE_BUFFER3_STATE_BUFFER
BDATA[0-23]
BDATA_V_SYNC
BDATA_H_SYNC
BDATA_EN
YUV_PIXCLK
R351
33
R352
33
R353
33
R354
22
+3.3V_STi
V_DDR_VREF
DDR_VTT
V_DDR_VREF
+2.6V_V_DDR
DDR_VTT
+2.6V_DDR
DDR_VTT
V_DDR_VTT
DDR_VREF
+2.6V_V_DDR
V_DDR_VTT
+2.6V_DDR
V_DDR_VTT
V_DDR_VTT
DDR_VTT
DDR_VREF
+3.3V
+3.3V
+3.3V
+3.3V
IC302
HYB25D256160CE-5
26
BA0
27
BA1
28
A10/AP
29
A0
30
A1
31
A2
32
A3
33
VDD_3
34
VSS_1
35
A4
36
A5
37
A6
38
A7
39
A8
40
A9
41
A11
42
NC_5/A12
43
NC_6
44
CKE
45
CK
46
CK
47
UDM
48
VSS_2
49
VREF
50
NC_7
17
NC_2/A13
3
VDDQ_1
6
VSSQ_1
16
LDQS
15
VDDQ_3
14
NC_1
13
DQ7
12
VSSQ_2
11
DQ6
10
DQ5
9
VDDQ_2
8
DQ4
7
DQ3
4
DQ1
5
DQ2
25
NC_4
24
CS0
23
RAS
2
DQ0
22
CAS
21
WE
1
VDD_1
20
LDM
19
NC_3
18
VDD_2
51
UDQS
52
VSSQ_3
53
NC_8
54
DQ8
55
VDDQ_4
56
DQ9
57
DQ10
58
VSSQ_4
59
DQ11
60
DQ12
61
VDDQ_5
62
DQ13
63
DQ14
64
VSSQ_5
65
DQ15
66
VSS_3
IC303
HYB25D256160CE-5
26
BA0
27
BA1
28
A10/AP
29
A0
30
A1
31
A2
32
A3
33
VDD_3
34
VSS_1
35
A4
36
A5
37
A6
38
A7
39
A8
40
A9
41
A11
42
NC_5/A12
43
NC_6
44
CKE
45
CK
46
CK
47
UDM
48
VSS_2
49
VREF
50
NC_7
17
NC_2/A13
3
VDDQ_1
6
VSSQ_1
16
LDQS
15
VDDQ_3
14
NC_1
13
DQ7
12
VSSQ_2
11
DQ6
10
DQ5
9
VDDQ_2
8
DQ4
7
DQ3
4
DQ1
5
DQ2
25
NC_4
24
CS0
23
RAS
2
DQ0
22
CAS
21
WE
1
VDD_1
20
LDM
19
NC_3
18
VDD_2
51
UDQS
52
VSSQ_3
53
NC_8
54
DQ8
55
VDDQ_4
56
DQ9
57
DQ10
58
VSSQ_4
59
DQ11
60
DQ12
61
VDDQ_5
62
DQ13
63
DQ14
64
VSSQ_5
65
DQ15
66
VSS_3
IC300
HYB25D256160CE-5
26
BA0
27
BA1
28
A10/AP
29
A0
30
A1
31
A2
32
A3
33
VDD_3
34
VSS_1
35
A4
36
A5
37
A6
38
A7
39
A8
40
A9
41
A11
42
NC_5/A12
43
NC_6
44
CKE
45
CK
46
CK
47
UDM
48
VSS_2
49
VREF
50
NC_7
17
NC_2/A13
3
VDDQ_1
6
VSSQ_1
16
LDQS
15
VDDQ_3
14
NC_1
13
DQ7
12
VSSQ_2
11
DQ6
10
DQ5
9
VDDQ_2
8
DQ4
7
DQ3
4
DQ1
5
DQ2
25
NC_4
24
CS0
23
RAS
2
DQ0
22
CAS
21
WE
1
VDD_1
20
LDM
19
NC_3
18
VDD_2
51
UDQS
52
VSSQ_3
53
NC_8
54
DQ8
55
VDDQ_4
56
DQ9
57
DQ10
58
VSSQ_4
59
DQ11
60
DQ12
61
VDDQ_5
62
DQ13
63
DQ14
64
VSSQ_5
65
DQ15
66
VSS_3
IC301
HYB25D256160CE-5
26
BA0
27
BA1
28
A10/AP
29
A0
30
A1
31
A2
32
A3
33
VDD_3
34
VSS_1
35
A4
36
A5
37
A6
38
A7
39
A8
40
A9
41
A11
42
NC_5/A12
43
NC_6
44
CKE
45
CK
46
CK
47
UDM
48
VSS_2
49
VREF
50
NC_7
17
NC_2/A13
3
VDDQ_1
6
VSSQ_1
16
LDQS
15
VDDQ_3
14
NC_1
13
DQ7
12
VSSQ_2
11
DQ6
10
DQ5
9
VDDQ_2
8
DQ4
7
DQ3
4
DQ1
5
DQ2
25
NC_4
24
CS0
23
RAS
2
DQ0
22
CAS
21
WE
1
VDD_1
20
LDM
19
NC_3
18
VDD_2
51
UDQS
52
VSSQ_3
53
NC_8
54
DQ8
55
VDDQ_4
56
DQ9
57
DQ10
58
VSSQ_4
59
DQ11
60
DQ12
61
VDDQ_5
62
DQ13
63
DQ14
64
VSSQ_5
65
DQ15
66
VSS_3
C301
0.01uF
C303
0.01uF
C318
0.01uF
C326
0.01uF
C329
0.1uF
C319
0.1uF
C320
0.1uF
C312
0.1uF
C315
0.1uF
C311
0.1uF
C313
0.1uF
C304
0.1uF
C307
0.1uF
C302
0.1uF
C306
0.1uF
C305
0.1uF
C321
0.1uF
C327
0.1uF
C328
0.1uF
C324
0.1uF
C360
0.1uF
R343
4.7K
R345
4.7K
AR314
100
AR330
100
AR306
100
AR308
100
AR331
100
AR312
100
AR316
100
AR317
100
AR311
100
AR309
100
AR338
100
AR315
100
AR335
100
AR329
100
AR307
100
AR326
100
AR310
100
AR305
100
AR336
100
AR337
100
AR327
100
AR334
100
AR333
100
AR328
100
AR332
100
AR313
100
IC310
S29JL064H90TA100
ST_8M_FLASH
26
CE
27
VSS1
28
OE
29
DQ0
30
DQ8
31
DQ1
32
DQ9
33
DQ2
34
DQ10
35
DQ3
36
DQ11
37
VCC
38
DQ4
39
DQ12
40
DQ5
41
DQ13
42
DQ6
43
DQ14
44
DQ7
45
DQ15/A-1
46
VSS2
47
BYTE
48
A16
17
A17
3
A13
6
A10
16
A18
15
RY/BY
14
WP/ACC
13
A21
12
RESET
11
WE
10
A20
9
A19
8
A8
7
A9
4
A12
5
A11
25
A0
24
A1
23
A2
2
A14
22
A3
21
A4
1
A15
20
A5
19
A6
18
A7
R310
100
R323
100
R314
100
R321
100
R312
100
R318
100
R313
100
R324
100
R329
100
R326
100
R316
100
R320
100
R319
100
R311
100
R328
100
R322
100
R350
100
OPT
IC304
24LC256-I/SM
3
A2
2
A1
4
VSS
1
A0
5
SDA
6
SCL
7
WP
8
VCC
C361
0.1uF
C362
0.1uF
C364
0.1uF
C363
0.1uF
R349
100
OPT
R355 33
R356
33
OPT
C369
10uF
C370
10uF
C371
10uF
C372
10uF
C365
10uF
C366
10uF
C367
10uF
C368
10uF
C373
10uF
C374
10uF
C375
10uF
C376
10uF
C351
10uF
C353
10uF
C350
10uF
C356
10uF
C355
10uF
C354
10uF
C352
10uF
C357
10uF
C377
10uF
C378
10uF
C379
10uF
C380
10uF
C381
10uF
C382
10uF
C383
10uF
C384
10uF
R357
200
R358
200
R359
200
R360
200
DDR_CK0
/DDR_CK0
DDR_CK0
/DDR_CK0
R361
200
R362 200
R363
200
R364
200
V_DDR_CK0
/V_DDR_CK0
V_DDR_CK0
/V_DDR_CK0
C308
0.1uF
C314
0.1uF
C330
0.1uF
C332
0.1uF
C322
0.1uF
C331 470pF
C323
470pF
C316
470pF
C309
470pF
R366
200
/DDR_CK0
DDR_CK0
/DDR_CK0
DDR_CK0
V_DDR_CK0
/V_DDR_CK0
R368
200
V_DDR_CK0
/V_DDR_CK0
C385
0.1uF
C386
0.1uF
C387
0.1uF
C388
0.1uF
C389
0.1uF
C390
0.1uF
C391
0.1uF
DDR_VTT
C392
0.1uF
C393
0.1uF
C394
0.1uF
C395
0.1uF
C396
0.1uF
C397
0.1uF
C398
0.1uF
V_DDR_VTT
R365
200
R367
200
EMI_ADDR[1-22]
EMI_DATA[0-15]
EMI_RDnotWR
/STi7100_Reset
WDOG_Reset
/FLASH_WP
EMI_notOE
EMI_notCSA
TP300
TP301TP302TP303
TP304TP305TP306TP307TP308TP309TP310TP311TP312TP313TP314TP315
TP316TP317TP318TP319
TP320TP321TP322TP323
TP324TP325
TP326TP327TP328TP329TP330TP331
TP332TP333TP334
TP335TP336TP337
TP338TP339TP340TP341TP342TP343TP344
TP345
TP346TP347
TP348TP349
TP350TP351
TP352
TP353
TP354
TP355
TP366
C310
10uF
6.3V
C325
10uF 6.3V
C300
10uF
6.3V
C317
10uF6.3V
AR325
33
AR322
33
AR323
33
AR320
33
AR324
33
AR321
33
C335
47uF
16V
C334
47uF
16V
C333
47uF
16V
C336
47uF
16V
+3.3V_STi
R347
1.2K
R348
1.2K
GND
GND
GND
GND
FLASH
EEPROM
Place at the junction of both CLK pars
Place at the junction of both CLK pars
3. ST DDR & FLASH Memory
To be close to VTT Resistors
To be close to VTT Resistors
IC300 side
IC302 side
Fibe
r Optic
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
L460
FI-C2012-682KJT
IC462
MC33078DR2G
3
INPUT1+
2
INPUT1-
4
VEE
1
OUTPUT1
5
INPUT2+
6
INPUT2-
7
OUTPUT2
8
VCC
LRCLK_DTV
HDMI_SCKLRCLK_MUX
3_STATE_BUFFER
IC410
TC74LCX157FT
3
2
4
1
6
5
7
89
10
11
12
13
14
15
16
HDMI_LRCH
SCLK_DTV
HDMI_LRCK
SCLK_MUX
PCMDATA_DTV
+3.3V
PCMDATA_MUX
R403
10K
Q402
2SC3875S
1
E
2
B
3
C
R407
12K
Q401
2SC3875S
1
E
2
B
3
C
Q400
2SC3875S
1
E
2
B
3
C
GND
Q460
2SA1504S
E
B
C
GND
GND
P_12V
5.0V
5.0V
SPDIF_OUT
R483
1K
ZD400
READY
R484
27
5.0V
C480
0.1uF
C474
0.1uF
C430
0.1uF
C469
0.1uF
16V
R414
1K
R415
1K
R448
100
R480
100
R446
100
R475
5.1K
C468
0.01uF
R422
4.7K
R481
0
R479
0
R416
0
R417
0
C434
READY
C433
READY
IC461
MC33078DR2G
3
INPUT1+
2
INPUT1-
4
VEE
1
OUTPUT1
5
INPUT2+
6
INPUT2-
7
OUTPUT2
8
VCC
C476
10uF
16V
C475
47uF
16V
R476
2K
C451
0.1uF
OPT
C452
0.1uF
OPT
C453
0.1uF
OPT
C454
0.1uF
OPT
JK400
JST1223-001
1
GND
2
VCC
3
VINPUT
4
FIX_POLE
C477
10uF
16V
+9V_CXA2069
AUDANA_GND
AUDANA_GND
AUDANA_GND
AUDANA_GND
AUDANA_GND
AUDANA_GND
R485
0
R498
0
AUDANA_GND
R499
0
AUDANA_GND
SPDIF_STI_OUT
SPDIF_MSP_OUT
SPDIF_OUT
SP_CVBS
CVBS
PIO2B6
PIO2B7
REC_8
AUD_ANAL-
AUD_ANAL+
AUD_ANAR+
AUD_ANAR-
AUD_ANA_VBG
DTV_ROUT
DTV_LOUT
JP400
JP401
TP400
TP401
TP402
TP403
TP404
TP405
TP418
TP419
TP420
TP421
TP422
TP423
TP424
TP425
TP426
TP427
R472
3.3K
R473
3.3K
R469
3.3K
R468
3.3K
R489
1K
R487
1K
R486
1K
R488
1K
R461
27
R463
27
R464
27
R462
27
L400
FI-C2012-682KJT
TP428
TP429TP430
TP431TP432
TP433
TP434TP435
TP436TP437
TP441
TP442
TP443
TP444
TP445
TP446
TP447
TP448
TP449
TP450
TP451
R438
0
R441
100
R439
100
C435
READY
C432
READY
C465
1000pF
C464
1000pF
C467
1000pF
C466
1000pF
TP406TP407
TP408
4Y
1Y
VCC
3A
3Y
ST
LOW
1A
SEL
GND
1B
2A
2B
I2S SWITCHING (DTV&HDMI)
HIGH
4A
3B
4B
2Y
TO MSP
SPDIF OPTIC JACK
OPTION
[SCART PIN8]
5.19V / 10.91V_1Kohm(LOAD)
4.89V / 9.09V_120ohm(LOAD)
% MUST BE PLACED NEAR IC100
4. I2S & ETC
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
L504
10uH
L502
HH-1M3216-501
IC511
SC2595STR
3
V_SENSE
2
GND
4
VREF
1
NC
5
VDDQ
6
AVCC
7
PVCC
8
VTT
IC510
SC2595STR
3
V_SENSE
2
GND
4
VREF
1
NC
5
VDDQ
6
AVCC
7
PVCC
8
VTT
C569
1000pF
R560
12K
R559
15K
1%
L500
HH-1M3216-501
CI_EN
GND
5.0V_CI
GND
GND
GND
GND
+3.3V
1.8V_HDMI
C597
100uF
16V
L507
HH-1M3216-501
V_DDR_VTT
V_DDR_VREF
DDR_VREF
DDR_VTT
+2.6V_V_DDR
+2.6V_VIDEO
+2.6V_SYS
+3.3V
+1.0V_STi7100
+3.3V
+2.6V_DDR
+2.6V_V_DDR
+2.6V_STi7100
+2.6V_SATA
+1.0V_SATA
1.8V_AMP
C596
100uF
16V
C525
0.1uF
C520
0.1uF
C516
0.1uF
C561
0.1uF
0.1uF
C594
C521
0.1uF
0.1uF
C595
C573
0.1uF
C545
0.1uF
C553
0.01uF
C571
0.01uF
C555
0.01uF
C568
0.01uF
+2.6V_SYS
+2.6V_VIDEO
C562
220uF
16V
C574
220uF
16V
+2.6V_DDR
C598
0.1uF
R562
10
C599
1000pF
50V
R570
10K
R571
91K
OPT
R572
82.5K
1/10W
1%
+3.3V
R576
10K
C536
0.1uF
16V
C538
0.1uF
16V
GND
C582
0.1uF
16V
C584
0.1uF
16V
R561
10K
+3.3V
GND
IC515
SC4215ISTRT
3
VIN
2
EN
4
NC_2
1
NC_1
5
NC_3
6
VO
7
ADJ
8
GND
IC516
SC4215ISTRT
3
VIN
2
EN
4
NC_2
1
NC_1
5
NC_3
6
VO
7
ADJ
8
GND
IC502
SC4215ISTRT
3
VIN
2
EN
4
NC_2
1
NC_1
5
NC_3
6
VO
7
ADJ
8
GND
GND
GND
GND
C572
330uF
4V
C560
330uF
4V
C522
100uF
16V
TP508
TP510
TP511
TP513
TP514
TP515
TP516
TP517
TP518
TP519
TP520 TP521
TP522
TP523
TP524
TP525
TP526
TP527
TP530
TP531
TP534
TP535
TP536 TP537
TP538 TP539
C539
100uF
16V
C580
330uF
4V
C566
330uF
4V
C583
100uF
16V
C523
100uF
16V
C537
100uF
16V
R575
47K
R565
47K
L508
HB-1M1608-501JT
R569
1.21K
1%
R574
105K
R577
105K
R563
1K
R573
1K
C558
100uF
16V
GND
R558
4.7K
1/10W
1%
IC513
BD9132MUV
1
SW_1
3
SW_3
7
PVCC_2
9
BST
10
VCC
11
GND
12
ADJ
13
ITH
14
NC_1
15
NC_2
16
NC_3
17
EN
18
PGND_1
19
PGND_2
20
PGND_3
5
SW_5
8
PVCC_3
6
PVCC_1
4
SW_4
2
SW_2
C510
0.1uF
GND
C511
0.1uF
GND
IC500
AZ1117H-1.8TRE1(EH13A)
2
OUTPUT
3
INPUT
1
ADJ/GND
R501
13K
1%
C517
100uF
16V
C509
0.1uF
16V
C549
100uF
16V
GND
L510
15uH
GND
C528
100uF
16V
D500
40V
MBRS340
GND
C502
0.01uF
+8V_MSP4450
C503
0.01uF
C501
1000pF
50V
GND
GND
IC505
KIA78R33F
1
VIN
2
VC
3
VOUT
4
NC
5
GND1
6
GND2
IC501
AZ1117H-1.8TRE1(EH13A)
2
OUTPUT
3
INPUT
1
ADJ/GND
GND
TUNER_3.3V_ON
R504
120K
C505
100uF
16V
TP506
GND
1.8V_TUNER
IC504
MP2355DN-LF-Z
3
VIN
2
BST
4
LX
1
SS
5
GND
6
FB
7
COMP
8
RUN
GND
C532
0.1uF
C551
0.1uF
16V
GND
C530
0.1uF
C524
0.1uF
16V
C507
100uF
16V
GND
GND
C508
0.1uF
16V
GND
GND
TP502
C506
100uF
16V
C550
0.1uF
16V
GND
5.0V
3.3V_TUNER
GND
C526
100uF
16V
+5VST_1
R578
100
GND
GND
GND
C518
0.1uF
16V
R502
22K
1%
+3.3V
GND
+5VST_3
Q502
G
D
S
TP509
R567
4.7K
Q504
2SC3875S
E
B
C
GND
+5VST_3
R564
1K
C542
0.1uF
Q503
2SC3875S
E
B
C
TP507
R557
4.7K
GND
R566
1K
5.0V_MSP
C543
0.1uF
Q501
G
D
S
TP540
L505
HH-1M3216-501
C544
0.1uF
GND
IC506
KIA78R05F
1
VIN
2
VC
3
VOUT
4
NC
5
GND1
6
GND2
R579
100
TUNER_3.3V_ON
GND
GND
GND
+5VST_3
C591
220uF
16V
TUNER_3.3V_ON
L501
UBW2012-121F
L503
UBW2012-121F
+3.3V
GND
R505
4.7K
TP541
Q507
G
D
S
TP542
R507
1K
C512
0.1uF
Q508
2SC3875S
E
B
C
GND
C513
0.1uF
3.3V_ON
R503
10K
1/10W
5%
+1.1V_STi_ON
R584
10K
1/10W
5%
R585
10K
1/10W
5%
READY
C592
1000pF
50V
READY
R582
33K
R583
33K
+3.3V
Q506
2SC3875S
E
B
C
+2.5V_STi_ON
+3.3V
R581
10K
Q505
2SC3875S
E
B
C
R580
10K
+2.5V_STi_ON_REG
+2.5V_STi_ON
+2.5V_STi_ON_REG
+2.5V_STi_ON_REG
RL_ON/PWR_ONOFF_2
R586
100
1/10W
5%
+3.3V_STi
L509
HH-1M3216-501
C514
100uF
16V
C515
0.1uF
R556
0
R506
0
R568
0
C504
22uF
16V
C519
22uF
16V
C535
22uF
16V
C575
22uF
16V
C579
22uF
16V
C581
22uF
16V
C593
22uF
16V
TP544
TP545
TP546
TP547
TP548
TP549
TP550
TP551
TP552
TP553
TP554
TP555
TP556
TP557
TP558
TP559
TP560
TP561
TP562
TP563
TP564
TP565
TP566
TP567
TP568
TP569
TP570
TP571
TP572
TP573
TP574
TP575
TP576
TP577
TP578
TP579
TP580
TP581
TP582
TP583
TP584
TP585
TP586
TP587
TP588
TP589
TP590
TP591
TP592
TP593
TP594
TP595
TP596
TP597
TP598
TP599
TP70
TP55
TP51
TP52
TP53
TP54
TP83
TP56
TP57
TP58
TP59
TP60
TP61
TP62
TP63
TP64
TP65
TP66
TP67
TP68
TP69
TP501
TP71
TP72
TP73
TP74
TP75
TP76
TP77
TP78
TP79
TP80
TP81
TP84
TP82
TP86
TP505
TP49
TP48
TP47
TP46
TP45
TP44
TP43
TP42
TP41
TP40
TP39
TP38
TP37
TP36
TP35
TP34
TP33
TP31
TP30
TP99
TP98
TP97
TP96
TP95
TP94
TP93
TP92
TP91
TP90
TP89
TP88
TP87
TP543
TP85
TP504
TP503
TP29
TP28
STi7109_Ext Core 2.5V
ST7019_Ext core 1.13volt
5. POWER BLOCK
Over current protection can be operated
1.8V for HDMI
3.3 volt for HDMI
5.0V For only C.I.
Vcc filter for Soft start
TUNER 3.3/1.8 volt
5.0 volt
3.3 volt
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
FE_TS_DATA_SYN
FE_TS_DATA[0]
FE_TS_DATA[1]
FE_TS_DATA[2]
FE_TS_DATA[3]
FE_TS_DATA[4]
FE_TS_DATA[5]
FE_TS_DATA[6]
FE_TS_DATA[7]
FE_TS_DATA_CLK
FE_TS_DATA_VAL
5V_TU
IC600
TPS2010ADR
READY
3
IN2
2
IN1
4
EN
1
GND
5
OUT1
6
OUT2
7
OUT3
8
OUT4
10
R657
SW_TU_SDA
5V_TU
BOOSTER
100uF
C638
C613
100uF
16V
C612
47uF
16V
READY
C637
4700pF
GND
SW_TU_SCL
Q604
2SC3875S
E
B
C
Q609
2SA1504S
E
B
C
Q603
2SC3875S
E
B
C
5V_TU
Q608
2SC3875S
E
B
C
L606
HH-1M3216-501
READY
L607
HH-1M3216-501
FE_TS_DATA[0-7],FE_TS_DATA_CLK,FE_TS_DATA_VAL,FE_TS_DATA_SYN
Q602
2SA1504S
C610
270pF
READY
3.3V_TUNER
Q606
2SA1504S
GND
C635
4700pF
5V_TU
GND
I2C_SCL1
I2C_SDA1
TUNER_RESET
FE_TS_DATA_VAL
5.0V
C642
47pF
READY
C641
47pF
READY
C616
0.1uF
C615
0.1uF
READY
C626
0.1uF
R659
0
READY
R654
0
READY
R613
0
C636
0.01uF
R653
10K
READY
R642
10K
R652
2K
READY
C604
10pF
C643
4.7uF
10V
Q607
2SA1504S
C608
100pF
C609
0.1uF
C606
0.1uF
C630
100uF
16V
C605
0.1uF
1.8V_TUNER
5V_TU
R606
33
R626
33
R605
33
R611
33
R610
33
R612
33
R604
33
R609
33
R603
33
R600
33
R608
33
R607
33
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
R627
100K
R629
100
C627
0.1uF
R625
33
R624
33
R640
0
C601
100pF
R636
4.7K
R639
82
R648
1K
R644
1K
R672
0
R641
READY
R649
150
R646
270
R651
0
R656
OPT
C603
0.01uF
2.2K
R658
10K
R655
3.3V_TUNER
TUNER_ERROR
TUNER_RESET
AGC_SPEED_CTL
/FE_RESET
SIF
TU_MAIN
TV_VOUT
TP600
TP601
TP602
TP603
TP604
TP605
TP606
TP607
TP608
TP609
TP610
TP611
TP612
TP613
TP614
TP615
TP616
TP617
TP618
TP619
TP620
TP621
TP622
TP623
TP624
TP625
TP626
TP627
TP629
TP630
TP631
TP632
TP633
TP634
TP635
TP636
TP637
TP638
TP639
TP641
TP642
AM_AUDIO
R660
0
R632
47
R633
47
R647
270
TP671
TP650
TP661
TP672
TP651
TP662
TP673
TP652
TP663
TP674
TP653
TP643
TP664
TP675
TP654
TP665
TP677
TP676
TP655
TP666
TP645
TP656
TP667
TP646
TP657
TP668
TP647
TP658
TP669
TP648
TP659
TP670
TP649
TP660
R637
470
R650
100
TU600
TDFV-G135D1
TUNER_G135D
1
ANT[5V]
2
BB[CTR]
3
GND_1
4
+B[5V]
5
NC_1
6
RF_AGC
7
TP[VT]
8
NC_2
9
GND_2
10
SDA_T
11
SCL_T
12
A
IF_1
13
AI F_
2
14
NC_3
15
VI DEO
16
AUDI O
17
SI F
18
SDA
19
SCL
20
RST
21
3. 3V
22
1. 8V
23
ERR
24
MCL
25
D7
26
D6
27
D5
28
D4
2
9
D3
30
D2
3
1
D1
35
SHI E
LD
32
D0
3
3
VAL
34
S
YNC
C633
47uF
16V
C623
47pF
GND
GND
C624
47pF
C644
100pF
READY
TP640
TP628
TP644
6.TUNER
to MSP
OPTION: RF AGC
(USE ONLY FOR SECAM)
Q603, R642
For SECAM
C604, C633
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
BDATA[0]
BDATA[1]
BDATA[2]
BDATA[3]
BDATA[4]
BDATA[5]
BDATA[6]
BDATA[7]
BDATA[8]
BDATA[9]
BDATA[10]
BDATA[11]
BDATA[12]
BDATA[13]
BDATA[14]
BDATA[15]
BDATA[16]
BDATA[17]
BDATA[18]
BDATA[19]
BDATA[20]
BDATA[21]
BDATA[22]
BDATA[23]
FSDATAU[0]
FSDATAU[1]
FSDATAU[2]
FSDATAU[3]
FSDATAU[4]
FSDATAU[5]
FSDATAU[6]
FSDATAU[7]
FSDATAU[8]
FSDATAU[9]
FSDATAU[10]
FSDATAU[11]
FSDATAU[12]
FSDATAU[13]
FSDATAU[14]
FSDATAU[15]
FSDATAU[16]
FSDATAU[17]
FSDATAU[18]
FSDATAU[19]
FSDATAU[20]
FSDATAU[21]
FSDATAU[22]
FSDATAU[23]
FSDATAU[24]
FSDATAU[25]
FSDATAU[26]
FSDATAU[27]
FSDATAU[28]
FSDATAU[29]
FSDATAU[30]
FSDATAU[31]
FSDATA[15]
FSDATA[14]
FSDATA[13]
FSDATA[12]
FSDATA[11]
FSDATA[10]
FSDATA[9]
FSDATA[8]
FSDATA[7]
FSDATA[6]
FSDATA[5]
FSDATA[4]
FSDATA[3]
FSDATA[2]
FSDATA[1]
FSDATA[0]
FSDATA[31]
FSDATA[30]
FSDATA[29]
FSDATA[28]
FSDATA[27]
FSDATA[26]
FSDATA[25]
FSDATA[24]
FSDATA[23]
FSDATA[22]
FSDATA[21]
FSDATA[20]
FSDATA[19]
FSDATA[18]
FSDATA[17]
FSDATA[16]
FSADDR[0-12]
FSADDRU[0-12],FSBKSELU[0-1],FSCKEU
FSADDRU[4]
FSADDRU[9]
FSADDRU[12]
FSADDRU[5]
FSADDRU[6]
FSADDRU[7]
FSADDRU[8]
FSCKEU
FSBKSELU[0]
FSBKSELU[1]
FSADDRU[0]
FSADDRU[1]
FSADDRU[2]
FSADDRU[10]
FSADDRU[3]
FSADDRU[11]
FSADDR[4]
FSADDR[9]
FSADDR[12]
FSADDR[5]
FSADDR[6]
FSADDR[7]
FSADDR[8]
FSADDR[0]
FSADDR[1]
FSADDR[2]
FSADDR[10]
FSADDR[3]
FSADDR[11]
FSADDRU[0]
FSADDRU[1]
FSADDRU[2]
FSADDRU[3]
FSADDRU[4]
FSADDRU[5]
FSADDRU[6]
FSADDRU[7]
FSADDRU[8]
FSADDRU[9]
FSADDRU[10]
FSADDRU[11]
FSADDRU[12]
FSCKEU
FSBKSELU[0]
FSBKSELU[1]
OCMADDR[21]
OCMADDR[20]
OCMADDR[19]
OCMADDR[18]
OCMADDR[17]
OCMADDR[16]
OCMADDR[15]
OCMADDR[14]
OCMADDR[13]
OCMADDR[12]
OCMADDR[11]
OCMADDR[10]
OCMADDR[9]
OCMADDR[8]
OCMADDR[7]
OCMADDR[6]
OCMADDR[5]
OCMADDR[4]
OCMADDR[3]
OCMADDR[2]
OCMADDR[1]
OCMADDR[0]
OCMADDR[1]
OCMADDR[2]
OCMADDR[3]
OCMADDR[4]
OCMADDR[5]
OCMADDR[6]
OCMADDR[7]
OCMADDR[8]
OCMADDR[10]
OCMADDR[11]
OCMADDR[12]
OCMADDR[0]
OCMADDR[9]
OCMADDR[13]
OCMADDR[14]
OCMADDR[15]
OCMADDR[16]
OCMADDR[17]
OCMADDR[18]
OCMADDR[19]
OCMDATA[15]
OCMDATA[14]
OCMDATA[13]
OCMDATA[12]
OCMDATA[11]
OCMDATA[10]
OCMDATA[9]
OCMDATA[8]
OCMDATA[7]
OCMDATA[6]
OCMDATA[5]
OCMDATA[4]
OCMDATA[3]
OCMDATA[2]
OCMDATA[1]
OCMDATA[0]
SCART1_R
CH1E+
RESET
FSDQS0
HDMI_CLK
ROM_CS
C1704
1uF
HD
SCL
SCART1_FB
UART0_TX
AR700
33
TUNER_3.3V_ON
YUV_PIXCLK
SDA_EEPR
FSCAS
OCMDATA[0-15]
FSDQS3
INV_CTL/VAVS_ON
SCL_5V
AR702
33
CEC_0
FSDQM3
R718 56
EEPROM_WP
MUTE_LINE_DTV
FSCS0
FSWE
BDATA[0-23]
AC_DET
FSDQM2
AR701
33
AGC_SPEED_CTL
BDATA_H_SYNC
Vbr_B
OCM_RE
1.8V_CORE_CTZ
3.3V_CTZ
SCL_EEPR
SDA_5V
SDA_EEPR
Vbr_A
R789
OPT
3.3V_ON
VGA_G
COR_STI_SWITCH
+2.5V_DDR_CTZ
FSDATA[0-31]
SCL
CKE-
UART0_RX
CH0E+
IR
BDATA_V_SYNC
R1712
33
MAIN_COUT
COMP_Y
HDMI_SEL1
FSCK+
RX4-
FSDQM0
SW_TU_SCL
VGA_R
C1704-*1
4.7uF
SCART1_B
CH0E-
BDATA_EN
AR704
33
SW_RESET
SDA
SDA
COMP_Pb
AR703
33
V_SYNC_PC
HDMI_SEL2
MUTE_LINE
R1714
33
FSDQS1
FSDQS2
1.8V_CORE_CTZ
AR706
33
R1716
33
FSBKSEL0
KEY_2
COMP_Pr
H_SYNC_PC
R723 56
OAD_CONT
C748-*1
4.7uF
FOR VITIAZ 2
X700
19.6608MHZ
R1711 33
CH4E-
AR705
33
R729 56
KEY_1
FSBKSEL1
FSDQM1
CH1E-
R1713 33
CEC_0
CKE+
SW_TU_SDA
R1718
33
OCMADDR[0-21]
UART1_RX
CH2E-
+3.3V
CH4E+
MAIN_V/YOUT
OCM_WE
C748
1uF
HD
FSADDR[0-12]
BOOSTER
FSCKE
R1715 33
CH2E+
C736
22uF
16V
RX4+
CH3E+
CH3E-
AR707
33
UART1_TX
3.3V_CTZ
FSRAS
FSCK-
VGA_B
SCL_EEPR
R727 56
FSVREF
DTV_RESET
3.3V_CTZ
SCART1_G
3.3V_CTZ
3.3V_CTZ
R1717 33
SCL_EEPR
MUTE_MAIN
RL_ON/PWR_ONOFF_2
SCART1_FB
3_STATE_BUFFER
R1738
10K
R1744
10K
R1747
10K
READY
R1767
10K
R1753
10K
R1749
10K
R1746
10K
READY
R1754
10K
R1745
10K
R1748
10K
READY
R1750
10K
R1755
10K
C711
0.1uF
C782
0.1uF
C786
0.1uF
C704
0.1uF
C764
0.1uF
C733
0.1uF
C716
0.1uF
C777
0.1uF
C710
0.1uF
C776
0.1uF
C754
0.1uF
C752
0.1uF
C760
0.1uF
C1702
0.1uF
C747
0.1uF
C756
0.1uF
C785
0.1uF
C745
0.1uF
C707
0.1uF
C734
0.1uF
C709
0.1uF
C712
0.1uF
C773
0.1uF
C763
0.1uF
C779
0.1uF
C729
0.1uF
C751
0.1uF
C722
0.1uF
C1703
0.1uF
C766
0.1uF
C703
0.1uF
C770
0.1uF
C757
0.1uF
C798
0.1uF
C742
0.1uF
C737
0.1uF
C783
0.1uF
C762
0.1uF
C792
0.1uF
C784
0.1uF
C732
0.1uF
C788
0.1uF
C780
0.1uF
C1700
0.1uF
C781
0.1uF
C750
0.1uF
C761
0.1uF
C775
0.1uF
C739
0.1uF
C726
0.1uF
C771
0.1uF
C767
0.1uF
C718
0.1uF
C759
0.1uF
C730
0.1uF
C787
0.1uF
C789
0.1uF
C769
0.1uF
C717
0.1uF
C753
0.1uF
C744
0.1uF
C746
0.1uF
C799
0.1uF
C721
0.1uF
C700
0.1uF
R701
4.7K
R709
4.7K
R703
4.7K
R708
4.7K
R702
4.7K
R1760 22
R757
22
R786
22
R785
100
R784
100
R782
100
R748
100
R770
100
R769
100
R780
100
R781
100
R755
390
HD
C795
22pF
C725
20pF
R755-*1
200
R790-*1
200
R783
0
R768
0
C794
0.01uF
C772
0.01uF
R1706 33
R1705 33
R1700 33
R793 33
R796 33
R1703 33
R792 33
R791 33
R1701 33
R798 33
R797 33
R794 33
R799 33
R795 33
R1704 33
R1707 33
R1708
33
R1720 33
R1721
33
R1719
33
R1709
33
R1710 33
R1709-*1
15
FULL_HD
R1708-*1 15
FULL_HD
R1742
10K
R1756
10K
R1757
10K
R1751
10K
R1752
10K
R1743
10K
R1741
10K
R1739
10K
R1740
10K
R1723
0
HD
R1722
0
HD
R1725
0
HD
R1724
0
HD
R1726
0
HD
R1727
0
HD
R1724-*1
22
FULL_HD
R1727-*1
22
FULL_HD
R1722-*1
22
FULL_HD
R1723-*1
22
FULL_HD
R1725-*1
22
FULL_HD
R1726-*1 22
FULL_HD
R715
22
R722
22
R716
22
R726
22
R725
22
R719
22
R714
22
R732
22
R717
22
R724
22
R728
22
R720
22
R721
22
R731
22
C708
0.1uF
C1701
0.1uF
C738
0.1uF
C755
0.1uF
C728
0.1uF
C791
0.1uF
C790 0.1uF
C749
0.1uF
C724
0.1uF
C768
0.1uF
C713
0.1uF
C778
0.1uF
C774
0.1uF
C714
0.1uF
C715
0.1uF
C706
0.1uF
R739
22
R745
100
R746
100
R749
100
R751
22
R752
22
R754
22
R764
22
R765
22
R766
22
R777
100
R772
100
R788
100
R779
100
R771
100
R787
100
R774
100
R773
100
R778
100
PANEL_CTL/DISP_EN
R737
22
R1729
22
FULL_HD
R1728
22
FULL_HD
R1733
22
FULL_HD
R1730
22
FULL_HD
R1731
22
FULL_HD
R1732
22
FULL_HD
R1735
22
FULL_HD
R1736
22
FULL_HD
R1734
22
FULL_HD
R1737
22
FULL_HD
SCL_5V
SDA_5V
IC701
24LC256-I/SM
3
A2
2
A1
4
VSS
1
A0
5
SDA
6
SCL
7
WP
8
VCC
R738
22
R1759 22
R1758 22
R743
100
R740
100
R741
22
SDA_EEPR
3.3V_CTZ
3.3V_CTZ_1
SCL_EYEQ
R1761
4.7K
R1762
4.7K
SDA_EYEQ
SDA_EYEQ
R1763
100
SCL_EYEQ
C723
330uF
4V
C758
10uF
6.3V
C796
10uF
6.3V
C701
10uF
6.3V
C743
10uF
6.3V
C705
10uF
6.3V
C740
10uF
6.3V
IC700
FLI8548H-LF-AB
A1P
AB1
A2P
AF1
A3P
AF4
A4P
AF7
AN
AD1
B1P
AC2
B2P
AE2
B3P
AE5
B4P
AE8
BN
AF3
C1P
AC1
C2P
AF2
C3P
AF5
C4P
AF8
CN
AF6
SV1P
AB2
SV2P
AE1
SV3P
AE4
SV4P
AE7
SVN
AF9
VOUT2
AC7
AIP_RAW_HS_CS
AF12
AIP_RAW_VS
AE12
EXT_OSD_VS
AD13
EXT_OSD_HS
AC13
EX_OSD_CLK
AF13
I2S_DOUT_1/GPIO
P3
I2S_DOUT_2/GPIO
P2
I2S_DOUT_3/GPIO
P1
DVI_RX0-
V1
DVI_RX0+
V2
DVI_RX1-
U1
DVI_RX1+
U2
DVI_RX2-
T1
DVI_RX2+
T2
DVI_RXC-
Y1
DVI_RXC+
Y2
DVI_REXT
R1
IPCLK0
N1
IPCLK1
P4
IPCLK2
M4
IPCLK3
L1
DIP_RAW_HS_CS
N2
DIP_EXT_CLAMP
M2
DIP_EXT_COAST
M3
DIP_CLEAN_HS_OUT
M1
BDATA0
B1
BDATA1
C3
BDATA2
C2
BDATA3
C1
BDATA4
D3
BDATA5
D2
BDATA6
D1
BDATA7
E3
BDATA8
E2
BDATA9
E1
BDATA10
F3
BDATA11
F2
BDATA12
F1
BDATA13
G3
BDATA14
G2
BDATA15
G1
BDATA16
H3
BDATA17
H2
BDATA18
H1
BDATA19
J3
BDATA20
J2
BDATA21
J1
BDATA22
K3
BDATA23
K2
DIP_BODD
N4
BVS
L2
BHS
L3
BHREF_DE
K1
XTAL
B26
TCLK
C26
PWM0
V24
PWM1
U23
PWM2[SPDIF]
U24
IR0
AB24
LBADC_IN6
AE11
LBADC_IN5
AF11
LBADC_IN4
AC10
LBADC_IN3
AD10
LBADC_IN2
AE10
LBADC_IN1
AF10
LBADC_RETURN
AD11
OCM_UDO_0
W26
OCM_UDI_0
W25
OCM_UDO_1
B2
OCM_UDI_1
B3
OCM_INT1
W23
OCM_INT2
Y24
OCM_TIMER1
W24
RESET
AD9
MSTR0_SCL
AA24
MSTR0_SDA
AA23
MSTR1_SCL
A3
MSTR1_SDA
A2
MSTR2_SCL
AB26
MSTR2_SDA
AB25
VGA0_SCL
AA26
VGA0_SDA
AA25
VGA1_SCL
Y26
VGA1_SDA
Y25
AVS_IN_SCL
AF14
AVS_IN_WORD_SEL
AD12
AVS_IN_DATA
AC12
AVS_OUT_DATA
AD14
AVS_OUT_SCL
AE13
AVS_OUT_WS
AE14
NC
M24
OBUFC_CLK
D25
TEST_EN
A1
SLAVE_SCL
V26
SLAVE_SDA
V25
JTAG_BS_EN
AC20
IC700
FLI8548H-LF-AB
FSDATA0
B4
FSDATA1
A4
FSDATA2
B5
FSDATA3
A5
FSDATA4
B7
FSDATA5
A7
FSDATA6
B8
FSDATA7
A8
FSDATA8
B9
FSDATA9
A9
FSDATA10
B10
FSDATA11
A10
FSDATA12
B12
FSDATA13
A12
FSDATA14
B13
FSDATA15
A13
FSDATA16
B15
FSDATA17
A15
FSDATA18
B16
FSDATA19
A16
FSDATA20
B18
FSDATA21
A18
FSDATA22
B19
FSDATA23
A19
FSDATA24
B20
FSDATA25
A20
FSDATA26
B21
FSDATA27
A21
FSDATA28
B23
FSDATA29
A23
FSDATA30
B24
FSDATA31
A24
FSADDR0
C18
FSADDR1
C17
FSADDR2
C16
FSADDR3
C15
FSADDR4
C13
FSADDR5
C10
FSADDR6
C8
FSADDR7
C7
FSADDR8
C6
FSADDR9
C12
FSADDR10
D16
FSADDR11
C14
FSADDR12
C11
FSCLKP
D5
FSCLKN
C5
FSCS0
D21
FSCS1
C22
FSDQS0
B6
FSDQS1
B11
FSDQS2
A17
FSDQS3
A22
FSDQM0
A6
FSDQM1
A11
FSDQM2
B17
FSDQM3
B22
FSWE
C23
FSCAS
D24
FSRAS
C24
FSCKE
C4
FSBKSEL0
C21
FSBKSEL1
C20
CH4P_LV_E/PD0[EBLU0]
N23
CH4N_LV_E/PD1[EBLU1]
N24
CH3P_LV_E/PD2[EBLU2]
N25
CH3N_LV_E/PD3[EBLU3]
N26
CLKP_LV_E/PD4[EBLU4]
L23
CLKN_LV_E/PD5[EBLU5]
L24
CH2P_LV_E/PD6[EBLU6]
L25
CH2N_LV_E/PD7[EBLU7]
L26
CH1P_LV_E/PD8[EGRN0]
K23
CH1N_LV_E/PD9[EGRN1]
K24
CH0P_LV_E/PD10[EGRN2]
K25
CH0N_LV_E/PD11[EGRN3]
K26
CH4P_LV_O/PD12[EGRN4]
J23
CH4N_LV_O/PD13[EGRN5]
J24
CH3P_LV_O/PD14[EGRN6]
G23
CH3N_LV_O/PD15[EGRN7]
G24
CLKP_LV_O/PD16[ERED0]
G25
CLKN_LV_O/PD17[ERED1]
G26
CH2P_LV_O/PD18[ERED2]
F23
CH2N_LV_O/PD19[ERED3]
F24
CH1P_LV_O/PD20[ERED4]
F25
CH1N_LV_O/PD21[ERED5]
F26
CH0P_LV_O/PD22[ERED6]
E23
CH0N_LV_O/PD23[ERED7]
E24
DCLK
P24
DHS
P25
DVS
R26
DEN
P26
OCMADDR21
AF15
OCMADDR20
AE15
OCMADDR19
AD15
OCMADDR18
AC15
OCMADDR17
AF16
OCMADDR16
AE16
OCMADDR15
AD16
OCMADDR14
AF17
OCMADDR13
AE17
OCMADDR12
AD17
OCMADDR11
AC17
OCMADDR10
AF18
OCMADDR9
AE18
OCMADDR8
AD18
OCMADDR7
AF19
OCMADDR6
AE19
OCMADDR5
AD19
OCMADDR4
AC19
OCMADDR3
AF20
OCMADDR2
AE20
OCMADDR1
AD20
OCMADDR0
AF21
OCMDATA15
AE21
OCMDATA14
AD21
OCMDATA13
AC21
OCMDATA12
AF22
OCMDATA11
AE22
OCMDATA10
AD22
OCMDATA9
AF23
OCMDATA8
AE23
OCMDATA7
AD23
OCMDATA6
AC23
OCMDATA5
AF24
OCMDATA4
AF25
OCMDATA3
AF26
OCMDATA2
AE24
OCMDATA1
AE25
OCMDATA0
AE26
OCM_RE
AC25
OCM_WE
AC26
ROM_CS
AD24
OCM_CS0
AD25
OCM_CS1
AD26
OCM_CS2
AC24
GPIO
N3
GPIO_42
T24
GPIO_43
T25
GPIO_44
T26
GPIO_45
R23
GPIO_46
R24
GPIO_47
R25
PPWR
U25
PBIAS
U26
RX2-
RX3+
RX1+
RX2+
RX1-
RX3-
RXCLK-
RXCLK+
RX0+
RX0-
IC700
FLI8548H-LF-AB
CORE_1.8_1
K10
CORE_1.8_2
K11
CORE_1.8_3
K16
CORE_1.8_4
K17
CORE_1.8_5
L11
CORE_1.8_6
L16
CORE_1.8_7
T11
CORE_1.8_8
T16
CORE_1.8_9
T17
CORE_1.8_10
U10
CORE_1.8_11
U11
CORE_1.8_12
U16
CORE_1.8_13
U17
I/O_3.3_1
E4
I/O_3.3_2
F4
I/O_3.3_3
G4
I/O_3.3_4
H4
I/O_3.3_5
J4
I/O_3.3_6
K4
I/O_3.3_7
L4
I/O_3.3_8
M23
I/O_3.3_9
P23
I/O_3.3_10
T23
I/O_3.3_11
V23
I/O_3.3_12
Y23
I/O_3.3_13
AB23
I/O_3.3_14
AC14
I/O_3.3_15
AC16
I/O_3.3_16
AC18
I/O_3.3_17
AC22
LBADC_33
AC9
DDR_2.5_1
D4
DDR_2.5_2
D6
DDR_2.5_3
D7
DDR_2.5_4
D8
DDR_2.5_5
D10
DDR_2.5_6
D11
DDR_2.5_7
D12
DDR_2.5_8
D13
DDR_2.5_9
D14
DDR_2.5_10
D15
DDR_2.5_11
D17
DDR_2.5_12
D18
DDR_2.5_13
D20
DDR_2.5_14
D22
DDR_2.5_15
D23
FSVREF_1
C9
FSVREF_2
C19
LVDS_PLL_3.3
H24
LVDS_3.3_1
E26
LVDS_3.3_2
H26
LVDS_3.3_3
J26
LVDS_3.3_4
M26
ADC_3.3
AD3
ADC_3.3_A
AD4
ADC_3.3_B
AD5
ADC_3.3_C
AD6
ADC_3.3_SC
AD7
RPLL_33
D26
RPLL_18
C25
VDD18_DLL
A14
ADC_1.8_1
AB4
ADC_1.8_2
AC4
ADC_1.8_3
AC5
DVI_1.8_1
U4
DVI_1.8_2
V4
DVI_1.8_3
W4
DVI_3.3_1
T3
DVI_3.3_2
U3
DVI_3.3_3
V3
3.3V_CTZ
+2.5V_DDR_CTZ
FSVREF
3.3V_CTZ
1.8V_CORE_CTZ
3.3V_CTZ
IC700
FLI8548H-LF-AB
D_GND_1
K12
D_GND_2
K13
D_GND_3
K14
D_GND_4
K15
D_GND_5
L10
D_GND_6
L12
D_GND_7
L13
D_GND_8
L14
D_GND_9
L15
D_GND_10
L17
D_GND_11
M10
D_GND_12
M11
D_GND_13
M12
D_GND_14
M13
D_GND_15
M14
D_GND_16
M15
D_GND_17
M16
D_GND_18
M17
D_GND_19
N10
D_GND_20
N11
D_GND_21
N12
D_GND_22
N13
D_GND_23
N14
D_GND_24
N15
D_GND_25
N16
D_GND_26
N17
D_GND_27
P10
D_GND_28
P11
D_GND_29
P12
D_GND_30
P13
D_GND_31
P14
D_GND_32
P15
D_GND_33
P16
D_GND_34
P17
D_GND_35
R10
D_GND_36
R11
D_GND_37
R12
D_GND_38
R13
D_GND_39
R14
D_GND_40
R15
D_GND_41
R16
D_GND_42
R17
D_GND_43
T10
D_GND_44
T12
D_GND_45
T13
D_GND_46
T14
D_GND_47
T15
D_GND_48
U12
D_GND_49
U13
D_GND_50
U14
D_GND_51
U15
DGND_ADC_1
AA1
DGND_ADC_2
AA2
DGND_ADC_3
AA3
DGND_ADC_4
AA4
LVDS_GND_1
E25
LVDS_GND_2
H25
LVDS_GND_3
J25
LVDS_GND_4
M25
LVDS_PLL_GND
H23
AGND_ADC_1
AB3
AGND_ADC_2
AC3
AGND_ADC_3
AC6
AGND_ADC_4
AC8
AGND_ADC_5
AD2
AGND_ADC_6
AD8
AGND_ADC_7
AE3
AGND_ADC_8
AE6
AGND_ADC_9
AE9
LBADC_GND
AC11
VSSA18_DLL
B14
PPLL_AGND_1
A25
PPLL_AGND_2
A26
PPLL_DGND
B25
FSVREFVSS_1
D9
FSVREFVSS_2
D19
GND_DVI_1
R2
GND_DVI_2
R3
GND_DVI_3
R4
GND_DVI_4
T4
GND_DVI_5
W1
GND_DVI_6
W2
GND_DVI_7
W3
GND_DVI_8
Y3
GND_DVI_9
Y4
3.3V_CTZ
R700
10K
R700-*1
2.7K
HD
RESET
R759
0
R758
0
R760
0
R706 10K
READY
R730
10K
READY
R707
10K
READY
3.3V_CTZ
TP700
TP701
TP702
TP703
TP704
TP705
TP706
TP707
TP708
TP709
TP710
TP711
TP712
TP713
TP716
TP717
TP718
TP719
TP720
TP721
TP722
TP723
TP724
TP725
TP726
TP727
TP728
TP729
TP730
TP731
TP732
TP752
TP753
TP754
TP755
TP756
TP757
3.3V_CTZ
R1783
0
HD
R1785
0
HD
R1787
0
HD
R1781
0
HD
R1786
22
FULL_HD
R1782
22
FULL_HD
R1788
22
FULL_HD
R1784
22
FULL_HD
R712 6.2K
SW_TU_SDA
5V_TU
R713
6.2K
SW_TU_SCL
R1787-*1
22
FULL_HD
R1781-*1
22
FULL_HD
R1783-*1
22
FULL_HD
R1785-*1
22
FULL_HD
R790
1.2K
HD
R750 22
R767
22
R753
22
R1779
0
R747
100
R744
100
R756
100
SW700
JTP-1127WEM
12
43
C1711
0.1uF
16V
READY
R742
100
R1764
100
GND
GND
C741
0.1uF
C765
0.1uF
5.0V_MSP_1
R1780
0
R710
3.3K
READY
R711
3.3K
READY
R763
200
R762
200
C719
12pF
BIT_SEL
MT8280_PRST
MT8280_PWN
MT8280_INT0
SCL_5V
R1778
0
L701
HH-1M3216-501
HDMI2_5V_DET
R1771
0
TP747
R1777
0
C1705
0.01uF
HDMI3_5V_DET
SDA_5V
HDMI1_5V_DET
GND
R736
0
+1.1V_STi_ON
TP746
HP_DET_S/W_1
R1772
0
R776
3.3K
R775
3.3K
R734
0
R735
0
+2.5V_STi_ON
R1776
0
TP742
R761
100
HP_DET_S/W_3
+5VST_3
IC702
M62320FP
3
SDA
2
SCL
4
D0
1
SO
6
D2
5
D1
7
D3
8
GND
9
D4
10
D5
11
D6
12
D7
13
VDD
14
CS2
15
CS1
16
CS0
R733
100
TP751
GND
HP_DET_S/W_2
R1770
0
PWM_BUZZ
MT8280_DWN
MT8280_FLASH_WP
TP767
if defined, R1788 for LCD
To be one hex file for LCD or PDP(Plasma)
Not stand_by power
I2C FULL-UP
Bootstrap
This is for
EEPROM
Vbr_A FOR FULL_HD
Vbr_B FOR FULL_HD
7. Cortez Plus
Stand_by power
RESET
IO EXPANDER IC
yright ⓒ 2008 LG Electronics. Inc. All right reserved.
for training and service purposes
LGE Internal Use Only
37/42/47/52LG7500
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